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Kuo-Jung Su3cff8422013-05-08 15:36:26 +08001/*
2 * Faraday I2C Controller
3 *
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
6 *
Tom Rini8dde4ca2013-07-24 09:25:40 -04007 * SPDX-License-Identifier: GPL-2.0+
Kuo-Jung Su3cff8422013-05-08 15:36:26 +08008 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <i2c.h>
13
14#include "fti2c010.h"
15
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080016#ifndef CONFIG_SYS_I2C_SPEED
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080017#define CONFIG_SYS_I2C_SPEED 5000
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080018#endif
19
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080020#ifndef CONFIG_SYS_I2C_SLAVE
21#define CONFIG_SYS_I2C_SLAVE 0
22#endif
23
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080024#ifndef CONFIG_FTI2C010_CLOCK
25#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080026#endif
27
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080028#ifndef CONFIG_FTI2C010_TIMEOUT
29#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
30#endif
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080031
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080032/* 7-bit dev address + 1-bit read/write */
33#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1)
34#define I2C_WR(dev) (((dev) << 1) & 0xfe)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080035
36struct fti2c010_chip {
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080037 struct fti2c010_regs *regs;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080038};
39
40static struct fti2c010_chip chip_list[] = {
41 {
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080042 .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080043 },
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080044#ifdef CONFIG_FTI2C010_BASE1
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080045 {
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080046 .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080047 },
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080048#endif
49#ifdef CONFIG_FTI2C010_BASE2
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080050 {
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080051 .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080052 },
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080053#endif
54#ifdef CONFIG_FTI2C010_BASE3
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080055 {
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080056 .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080057 },
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080058#endif
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080059};
60
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080061static int fti2c010_reset(struct fti2c010_chip *chip)
62{
63 ulong ts;
64 int ret = -1;
65 struct fti2c010_regs *regs = chip->regs;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080066
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080067 writel(CR_I2CRST, &regs->cr);
68 for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
69 if (!(readl(&regs->cr) & CR_I2CRST)) {
70 ret = 0;
71 break;
72 }
73 }
74
75 if (ret)
76 printf("fti2c010: reset timeout\n");
77
78 return ret;
79}
80
81static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080082{
83 int ret = -1;
84 uint32_t stat, ts;
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080085 struct fti2c010_regs *regs = chip->regs;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080086
Kuo-Jung Sue6d3ab82013-12-02 16:02:56 +080087 for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
Kuo-Jung Su3cff8422013-05-08 15:36:26 +080088 stat = readl(&regs->sr);
89 if ((stat & mask) == mask) {
90 ret = 0;
91 break;
92 }
93 }
94
95 return ret;
96}
97
Kuo-Jung Su49f4c762013-12-02 16:02:57 +080098static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
99 unsigned int speed)
100{
101 struct fti2c010_regs *regs = chip->regs;
102 unsigned int clk = CONFIG_FTI2C010_CLOCK;
103 unsigned int gsr = 0;
104 unsigned int tsr = 32;
105 unsigned int div, rate;
106
107 for (div = 0; div < 0x3ffff; ++div) {
108 /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
109 rate = clk / (2 * (div + 2) + gsr);
110 if (rate <= speed)
111 break;
112 }
113
114 writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), &regs->tgsr);
115 writel(CDR_DIV(div), &regs->cdr);
116
117 return rate;
118}
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800119
120/*
121 * Initialization, must be called once on start up, may be called
122 * repeatedly to change the speed and slave addresses.
123 */
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800124static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800125{
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800126 struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800127
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800128 if (adap->init_done)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800129 return;
130
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800131#ifdef CONFIG_SYS_I2C_INIT_BOARD
132 /* Call board specific i2c bus reset routine before accessing the
133 * environment, which might be in a chip on that bus. For details
134 * about this problem see doc/I2C_Edge_Conditions.
135 */
136 i2c_init_board();
137#endif
138
139 /* master init */
140
141 fti2c010_reset(chip);
142
143 set_i2c_bus_speed(chip, speed);
144
145 /* slave init, don't care */
146
147#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
148 /* Call board specific i2c bus reset routine AFTER the bus has been
149 * initialized. Use either this callpoint or i2c_init_board;
150 * which is called before fti2c010_init operations.
151 * For details about this problem see doc/I2C_Edge_Conditions.
152 */
153 i2c_board_late_init();
154#endif
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800155}
156
157/*
158 * Probe the given I2C chip address. Returns 0 if a chip responded,
159 * not 0 on failure.
160 */
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800161static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800162{
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800163 struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
164 struct fti2c010_regs *regs = chip->regs;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800165 int ret;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800166
167 /* 1. Select slave device (7bits Address + 1bit R/W) */
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800168 writel(I2C_WR(dev), &regs->dr);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800169 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800170 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800171 if (ret)
172 return ret;
173
174 /* 2. Select device register */
175 writel(0, &regs->dr);
176 writel(CR_ENABLE | CR_TBEN, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800177 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800178
179 return ret;
180}
181
Kuo-Jung Suc7276182013-12-02 16:02:58 +0800182static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
183{
184 int i, shift;
185
186 if (!buf || alen <= 0)
187 return;
188
189 /* MSB first */
190 i = 0;
191 shift = (alen - 1) * 8;
192 while (alen-- > 0) {
193 buf[i] = (u8)(addr >> shift);
194 shift -= 8;
195 }
196}
197
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800198static int fti2c010_read(struct i2c_adapter *adap,
199 u8 dev, uint addr, int alen, uchar *buf, int len)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800200{
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800201 struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
202 struct fti2c010_regs *regs = chip->regs;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800203 int ret, pos;
Kuo-Jung Sudccacbe2013-12-30 17:20:57 +0800204 uchar paddr[4] = { 0 };
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800205
Kuo-Jung Suc7276182013-12-02 16:02:58 +0800206 to_i2c_addr(paddr, addr, alen);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800207
208 /*
209 * Phase A. Set register address
210 */
211
212 /* A.1 Select slave device (7bits Address + 1bit R/W) */
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800213 writel(I2C_WR(dev), &regs->dr);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800214 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800215 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800216 if (ret)
217 return ret;
218
219 /* A.2 Select device register */
220 for (pos = 0; pos < alen; ++pos) {
221 uint32_t ctrl = CR_ENABLE | CR_TBEN;
222
223 writel(paddr[pos], &regs->dr);
224 writel(ctrl, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800225 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800226 if (ret)
227 return ret;
228 }
229
230 /*
231 * Phase B. Get register data
232 */
233
234 /* B.1 Select slave device (7bits Address + 1bit R/W) */
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800235 writel(I2C_RD(dev), &regs->dr);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800236 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800237 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800238 if (ret)
239 return ret;
240
241 /* B.2 Get register data */
242 for (pos = 0; pos < len; ++pos) {
243 uint32_t ctrl = CR_ENABLE | CR_TBEN;
244 uint32_t stat = SR_DR;
245
246 if (pos == len - 1) {
247 ctrl |= CR_NAK | CR_STOP;
248 stat |= SR_ACK;
249 }
250 writel(ctrl, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800251 ret = fti2c010_wait(chip, stat);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800252 if (ret)
253 break;
254 buf[pos] = (uchar)(readl(&regs->dr) & 0xFF);
255 }
256
257 return ret;
258}
259
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800260static int fti2c010_write(struct i2c_adapter *adap,
261 u8 dev, uint addr, int alen, u8 *buf, int len)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800262{
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800263 struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
264 struct fti2c010_regs *regs = chip->regs;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800265 int ret, pos;
Kuo-Jung Sudccacbe2013-12-30 17:20:57 +0800266 uchar paddr[4] = { 0 };
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800267
Kuo-Jung Suc7276182013-12-02 16:02:58 +0800268 to_i2c_addr(paddr, addr, alen);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800269
270 /*
271 * Phase A. Set register address
272 *
273 * A.1 Select slave device (7bits Address + 1bit R/W)
274 */
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800275 writel(I2C_WR(dev), &regs->dr);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800276 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800277 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800278 if (ret)
279 return ret;
280
281 /* A.2 Select device register */
282 for (pos = 0; pos < alen; ++pos) {
283 uint32_t ctrl = CR_ENABLE | CR_TBEN;
284
285 writel(paddr[pos], &regs->dr);
286 writel(ctrl, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800287 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800288 if (ret)
289 return ret;
290 }
291
292 /*
293 * Phase B. Set register data
294 */
295 for (pos = 0; pos < len; ++pos) {
296 uint32_t ctrl = CR_ENABLE | CR_TBEN;
297
298 if (pos == len - 1)
299 ctrl |= CR_STOP;
300 writel(buf[pos], &regs->dr);
301 writel(ctrl, &regs->cr);
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800302 ret = fti2c010_wait(chip, SR_DT);
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800303 if (ret)
304 break;
305 }
306
307 return ret;
308}
309
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800310static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
311 unsigned int speed)
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800312{
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800313 struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
314 int ret;
315
316 fti2c010_reset(chip);
317 ret = set_i2c_bus_speed(chip, speed);
318
319 return ret;
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800320}
321
322/*
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800323 * Register i2c adapters
Kuo-Jung Su3cff8422013-05-08 15:36:26 +0800324 */
Kuo-Jung Su49f4c762013-12-02 16:02:57 +0800325U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
326 fti2c010_write, fti2c010_set_bus_speed,
327 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
328 0)
329#ifdef CONFIG_FTI2C010_BASE1
330U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
331 fti2c010_write, fti2c010_set_bus_speed,
332 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
333 1)
334#endif
335#ifdef CONFIG_FTI2C010_BASE2
336U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
337 fti2c010_write, fti2c010_set_bus_speed,
338 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
339 2)
340#endif
341#ifdef CONFIG_FTI2C010_BASE3
342U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
343 fti2c010_write, fti2c010_set_bus_speed,
344 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
345 3)
346#endif