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wdenkfabd46a2004-07-10 23:11:10 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the CERF250 board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenkfabd46a2004-07-10 23:11:10 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38#define CONFIG_CERF250 1 /* on Cerf PXA Board */
39#define BOARD_LATE_INIT 1
40#define CONFIG_BAUDRATE 38400
Marek Vasutcaeb8c02010-10-20 18:56:41 +020041#define CONFIG_SYS_TEXT_BASE 0x0
wdenkfabd46a2004-07-10 23:11:10 +000042
Wolfgang Denk53677ef2008-05-20 16:00:29 +020043#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenkfabd46a2004-07-10 23:11:10 +000044
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020045/* we will never enable dcache, because we have to setup MMU first */
46#define CONFIG_SYS_NO_DCACHE
47
wdenkfabd46a2004-07-10 23:11:10 +000048/*
49 * Size of malloc() pool
50 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenkfabd46a2004-07-10 23:11:10 +000052
53/*
54 * Hardware drivers
55 */
Ben Warren7194ab82009-10-04 22:37:03 -070056#define CONFIG_NET_MULTI
57#define CONFIG_SMC91111
wdenkfabd46a2004-07-10 23:11:10 +000058#define CONFIG_SMC91111_BASE 0x04000300
59#define CONFIG_SMC_USE_32_BIT
60
61/*
62 * select serial console configuration
63 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020064#define CONFIG_PXA_SERIAL
wdenkfabd46a2004-07-10 23:11:10 +000065#define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */
66
67/* allow to overwrite serial and ethaddr */
68#define CONFIG_ENV_OVERWRITE
wdenkfabd46a2004-07-10 23:11:10 +000069
Jon Loeliger37e4f242007-07-04 22:31:56 -050070/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050080 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
wdenkfabd46a2004-07-10 23:11:10 +000084
85#define CONFIG_BOOTDELAY 3
86#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2
87#define CONFIG_NETMASK 255.255.255.0
88#define CONFIG_IPADDR 192.168.0.5
89#define CONFIG_SERVERIP 192.168.0.2
90#define CONFIG_BOOTCOMMAND "bootm 0xC0000"
91#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
92#define CONFIG_CMDLINE_TAG
93
Jon Loeliger37e4f242007-07-04 22:31:56 -050094#if defined(CONFIG_CMD_KGDB)
wdenkfabd46a2004-07-10 23:11:10 +000095#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
96#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
97#endif
98
99/*
100 * Miscellaneous configurable options
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_HUSH_PARSER 1
103#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkfabd46a2004-07-10 23:11:10 +0000104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_LONGHELP /* undef to save memory */
106#ifdef CONFIG_SYS_HUSH_PARSER
107#define CONFIG_SYS_PROMPT "uboot$ " /* Monitor Command Prompt */
wdenkfabd46a2004-07-10 23:11:10 +0000108#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkfabd46a2004-07-10 23:11:10 +0000110#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfabd46a2004-07-10 23:11:10 +0000113 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
115#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
116#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenkfabd46a2004-07-10 23:11:10 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
119#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkfabd46a2004-07-10 23:11:10 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
wdenkfabd46a2004-07-10 23:11:10 +0000122
Micha Kalfon94a33122009-02-11 19:50:11 +0200123#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
wdenkfabd46a2004-07-10 23:11:10 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfabd46a2004-07-10 23:11:10 +0000127
128
129/*
130 * Stack sizes
131 *
132 * The stack sizes are set up in start.S using the settings below
133 */
134#define CONFIG_STACKSIZE (128*1024) /* regular stack */
135#ifdef CONFIG_USE_IRQ
136#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
137#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
138#endif
139
140/*
141 * Physical Memory Map
142 */
Marek Vasutcaeb8c02010-10-20 18:56:41 +0200143#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200144#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
145#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
wdenkfabd46a2004-07-10 23:11:10 +0000146
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200147#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
148#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
149#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
150#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
151#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
wdenkfabd46a2004-07-10 23:11:10 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_DRAM_BASE 0xa0000000
154#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkfabd46a2004-07-10 23:11:10 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkfabd46a2004-07-10 23:11:10 +0000157
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200158#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200159#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200160
wdenkfabd46a2004-07-10 23:11:10 +0000161/*
162 * GPIO settings
163 */
164
165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_GPSR0_VAL 0x00408030
167#define CONFIG_SYS_GPSR1_VAL 0x00BFA882
168#define CONFIG_SYS_GPSR2_VAL 0x0001C000
169#define CONFIG_SYS_GPCR0_VAL 0xC0031100
170#define CONFIG_SYS_GPCR1_VAL 0xFC400300
171#define CONFIG_SYS_GPCR2_VAL 0x00003FFF
172#define CONFIG_SYS_GPDR0_VAL 0xC0439330
173#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB82
174#define CONFIG_SYS_GPDR2_VAL 0x0001FFFF
175#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
176#define CONFIG_SYS_GAFR0_U_VAL 0xA5000010
177#define CONFIG_SYS_GAFR1_L_VAL 0x60008018
178#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
179#define CONFIG_SYS_GAFR2_L_VAL 0xAAA0000A
180#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkfabd46a2004-07-10 23:11:10 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_PSSR_VAL 0x20
wdenkfabd46a2004-07-10 23:11:10 +0000183
Marek Vasutcaeb8c02010-10-20 18:56:41 +0200184#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
185#define CONFIG_SYS_CKEN 0x0
186
wdenkfabd46a2004-07-10 23:11:10 +0000187/*
188 * Memory settings
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MSC0_VAL 0x12447FF0
191#define CONFIG_SYS_MSC1_VAL 0x12BC5554
192#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
193#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
194#define CONFIG_SYS_MDREFR_VAL 0x03CDC017
195#define CONFIG_SYS_MDMRS_VAL 0x00000000
Marek Vasutcaeb8c02010-10-20 18:56:41 +0200196#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
197#define CONFIG_SYS_SXCNFG_VAL 0x00000000
wdenkfabd46a2004-07-10 23:11:10 +0000198
199/*
200 * PCMCIA and CF Interfaces
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_MECR_VAL 0x00000000
203#define CONFIG_SYS_MCMEM0_VAL 0x00010504
204#define CONFIG_SYS_MCMEM1_VAL 0x00010504
205#define CONFIG_SYS_MCATT0_VAL 0x00010504
206#define CONFIG_SYS_MCATT1_VAL 0x00010504
207#define CONFIG_SYS_MCIO0_VAL 0x00004715
208#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenkfabd46a2004-07-10 23:11:10 +0000209
210#define _LED 0x08000010 /*check this */
211#define LED_BLANK 0x08000040
212#define LED_GPIO 0x10
213
214/*
215 * FLASH and environment organization
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
218#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkfabd46a2004-07-10 23:11:10 +0000219
220/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
222#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkfabd46a2004-07-10 23:11:10 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_LEN 0x40000 /* 256 KiB */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200225#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200227#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkfabd46a2004-07-10 23:11:10 +0000228
229
230#endif /* __CONFIG_H */