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Wolfgang Denk7ce343e2006-10-09 00:48:57 +02001/*
2 * Copyright (C) 2006 Embedded Planet, LLC.
3 *
4 * U-Boot configuration for Embedded Planet EP82xxM boards.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28#define CONFIG_MPC8260
29#define CPU_ID_STR "MPC8270"
30
Wolfgang Denkf836e412006-10-20 16:12:14 +020031#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020032 /* 256MB SDRAM / 64MB FLASH */
33
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0xFFF00000
35
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020036#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
37
38/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
39#define CONFIG_ENV_OVERWRITE
40
41/*
42 * Select serial console configuration
43 *
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC).
47 */
48#define CONFIG_CONS_ON_SMC /* Console is on SMC */
49#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50#undef CONFIG_CONS_NONE /* It's not on external UART */
51#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_BCSR 0xFA000000
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020054
55/*
56 * Select ethernet configuration
57 *
58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
59 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
60 * SCC, 1-3 for FCC)
61 *
62 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
Jon Loeliger639221c2007-07-09 17:15:49 -050063 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
64 * must be unset.
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020065 */
66#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
67#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
68#undef CONFIG_ETHER_NONE /* No external Ethernet */
69
70#define CONFIG_NET_MULTI
71
72#define CONFIG_ETHER_ON_FCC2
73#define CONFIG_ETHER_ON_FCC3
74
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
76#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
77#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
78#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_CPMFCR_RAMTYPE 0
81#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020082
83#define CONFIG_MII /* MII PHY management */
84#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
85
86/*
87 * GPIO pins used for bit-banged MII communications
88 */
89#define MDIO_PORT 0 /* Not used - implemented in BCSR */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
92#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
93#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
96 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
99 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200100
101#define MIIDELAY udelay(1)
102
103
104#ifndef CONFIG_8260_CLKIN
105#define CONFIG_8260_CLKIN 66000000 /* in Hz */
106#endif
107
108#define CONFIG_BAUDRATE 115200
109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200111
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200112
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500113/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500114 * BOOTP options
115 */
116#define CONFIG_BOOTP_BOOTFILESIZE
117#define CONFIG_BOOTP_BOOTPATH
118#define CONFIG_BOOTP_GATEWAY
119#define CONFIG_BOOTP_HOSTNAME
120
121
122/*
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500123 * Command line configuration.
124 */
125#include <config_cmd_default.h>
126
127
128#define CONFIG_CMD_DHCP
129#define CONFIG_CMD_ECHO
130#define CONFIG_CMD_I2C
131#define CONFIG_CMD_IMMAP
132#define CONFIG_CMD_MII
133#define CONFIG_CMD_PING
134#define CONFIG_CMD_DATE
135#define CONFIG_CMD_DTT
136#define CONFIG_CMD_EEPROM
137#define CONFIG_CMD_PCI
138#define CONFIG_CMD_DIAG
139
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200140
141#define CONFIG_ETHADDR 00:10:EC:00:88:65
142#define CONFIG_HAS_ETH1
143#define CONFIG_ETH1ADDR 00:10:EC:80:88:65
144#define CONFIG_IPADDR 10.0.0.245
145#define CONFIG_HOSTNAME EP82xxM
146#define CONFIG_SERVERIP 10.0.0.26
147#define CONFIG_GATEWAYIP 10.0.0.1
148#define CONFIG_NETMASK 255.255.255.0
149#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200150#define CONFIG_ENV_IN_OWN_SECT 1
Wolfgang Denk8078f1a2006-10-28 02:28:02 +0200151#define CONFIG_AUTO_COMPLETE 1
Heiko Schocher48690d82010-07-20 17:45:02 +0200152#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3"
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200153
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500154#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200155#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
156#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
157#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
158#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
159#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
160#endif
161
162#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
163#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
164
165/*
166 * Miscellaneous configurable options
167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_HUSH_PARSER
169#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
170#define CONFIG_SYS_LONGHELP /* undef to save memory */
171#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500172#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200174#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200176#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
178#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
179#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
182#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200189
190/*-----------------------------------------------------------------------
191 * Environment
192 *----------------------------------------------------------------------*/
193/*
194 * Define here the location of the environment variables (FLASH or EEPROM).
195 * Note: DENX encourages to use redundant environment in FLASH.
196 */
197#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200198#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200199#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200200#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200201#endif
202
203/*-----------------------------------------------------------------------
204 * FLASH related
205 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_BASE 0xFC000000
207#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200208#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
210#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
211#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200212
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200213#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200214#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200216#endif /* CONFIG_ENV_IS_IN_FLASH */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200217
218/*-----------------------------------------------------------------------
219 * I2C
220 *----------------------------------------------------------------------*/
221/* EEPROM Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_EEPROM_SIZE 0x1000
223#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
224#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
225#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
226#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200227
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200228#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200229#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
230#define CONFIG_ENV_OFFSET 0x0
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200231#endif /* CONFIG_ENV_IS_IN_EEPROM */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200232
233/* RTC Configuration */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200234#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200236#define CONFIG_M41T11_BASE_YEAR 1900
237
238/* I2C SYSMON (LM75) */
239#define CONFIG_DTT_LM75 1
240#define CONFIG_DTT_SENSORS {0}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_DTT_MAX_TEMP 70
242#define CONFIG_SYS_DTT_LOW_TEMP -30
243#define CONFIG_SYS_DTT_HYSTERESIS 3
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200244
245/*-----------------------------------------------------------------------
246 * NVRAM Configuration
247 *-----------------------------------------------------------------------
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
250#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200251
252
253/*-----------------------------------------------------------------------
254 * PCI stuff
255 *-----------------------------------------------------------------------
256 */
257/* General PCI */
258#define CONFIG_PCI /* include pci support */
259#define CONFIG_PCI_PNP /* do pci plug-and-play */
260#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
261#define CONFIG_PCI_BOOTDELAY 0
262
263/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
265#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
266#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200267 PICMR_PREFETCH_EN)
268
269/*
270 * These are the windows that allow the CPU to access PCI address space.
271 * All three PCI master windows, which allow the CPU to access PCI
272 * prefetch, non prefetch, and IO space (see below), must all fit within
273 * these windows.
274 */
275
276/*
277 * Master window that allows the CPU to access PCI Memory (prefetch).
278 * This window will be setup with the second set of Outbound ATU registers
279 * in the bridge.
280 */
281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
283#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
284#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
285#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
286#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200287
288/*
289 * Master window that allows the CPU to access PCI Memory (non-prefetch).
290 * This window will be setup with the second set of Outbound ATU registers
291 * in the bridge.
292 */
293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
295#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
296#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
297#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
298#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200299
300/*
301 * Master window that allows the CPU to access PCI IO space.
302 * This window will be setup with the first set of Outbound ATU registers
303 * in the bridge.
304 */
305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
307#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
308#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
309#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
310#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200311
312
313/* PCIBR0 - for PCI IO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
315#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200316/* PCIBR1 - prefetch and non-prefetch regions joined together */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
318#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200319
320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_DIRECT_FLASH_TFTP
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200322
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500323#if defined(CONFIG_CMD_JFFS2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_JFFS2_FIRST_BANK 0
325#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
326#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
327#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
328#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
329#define CONFIG_SYS_JFFS_CUSTOM_PART
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500330#endif
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200331
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500332#if defined(CONFIG_CMD_I2C)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200333#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
335#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500336#endif
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200337
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200338#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
340#define CONFIG_SYS_RAMBOOT
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200341#endif
342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
346#define CONFIG_SYS_IMMR 0xF0000000
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200349#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200350#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200352
353
354/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200356/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_HRCW_SLAVE1 0
358#define CONFIG_SYS_HRCW_SLAVE2 0
359#define CONFIG_SYS_HRCW_SLAVE3 0
360#define CONFIG_SYS_HRCW_SLAVE4 0
361#define CONFIG_SYS_HRCW_SLAVE5 0
362#define CONFIG_SYS_HRCW_SLAVE6 0
363#define CONFIG_SYS_HRCW_SLAVE7 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200364
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
366#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500369#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200371#endif
372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_HID0_INIT 0
374#define CONFIG_SYS_HID0_FINAL 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_HID2 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_SIUMCR 0x02610000
379#define CONFIG_SYS_SYPCR 0xFFFF0689
380#define CONFIG_SYS_BCR 0x8080E000
381#define CONFIG_SYS_SCCR 0x00000001
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_RMR 0
384#define CONFIG_SYS_TMCNTSC 0x000000C3
385#define CONFIG_SYS_PISCR 0x00000083
386#define CONFIG_SYS_RCCR 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_MPTPR 0x0A00
389#define CONFIG_SYS_PSDMR 0xC432246E
390#define CONFIG_SYS_PSRT 0x32
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_SDRAM_BASE 0x00000000
393#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
394#define CONFIG_SYS_SDRAM_OR 0xF0002900
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
397#define CONFIG_SYS_OR0_PRELIM 0xFC000882
398#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR | 0x00001001)
399#define CONFIG_SYS_OR4_PRELIM 0xFFF00050
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200400
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200402
403#endif /* __CONFIG_H */