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Heiko Schocherca43ba12007-01-11 15:44:44 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
4 *
5 * From:
6 * (C) Copyright 2003
7 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#undef USE_VGA_GRAPHICS
32
33/* Memory Map
Wolfgang Denk6d3e0102007-01-16 18:30:50 +010034 * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
35 * 0x74000000 .... 0x740FFFFF -> CS#6
36 * 0x74100000 .... 0x741FFFFF -> CS#7
37 * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
38 * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
39 * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
40 * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
41 * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
42 * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
43 * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
44 * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
45 *
46 * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
47 * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
48 * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
49 * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
50 * 0xEED00000 .... 0xEED00003 -> PCI-Bus
51 * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
52 * 0xEF40003F .... 0xEF5FFFFF -> reserved
53 * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
54 * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
55 * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
56 * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
57 * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
58 * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
59 */
Heiko Schocherca43ba12007-01-11 15:44:44 +010060
Wolfgang Denk9045f332007-06-08 10:24:58 +020061#define CONFIG_SC3 1
Heiko Schocherca43ba12007-01-11 15:44:44 +010062#define CONFIG_4xx 1
63#define CONFIG_405GP 1
64
Wolfgang Denk2ae18242010-10-06 09:05:45 +020065#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
66
Heiko Schocherca43ba12007-01-11 15:44:44 +010067#define CONFIG_BOARD_EARLY_INIT_F 1
Peter Tyser3a8f28d2009-09-16 22:03:07 -050068#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
Heiko Schocherca43ba12007-01-11 15:44:44 +010069
70/*
Wolfgang Denk6d3e0102007-01-16 18:30:50 +010071 * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
72 * If undefined, IDE access uses a seperat emulation with higher access speed.
Heiko Schocherca43ba12007-01-11 15:44:44 +010073 * Consider to inform your Linux IDE driver about the different addresses!
Jon Loeliger639221c2007-07-09 17:15:49 -050074 * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
Heiko Schocherca43ba12007-01-11 15:44:44 +010075 */
76#define IDE_USES_ISA_EMULATION
77
78/*-----------------------------------------------------------------------
79 * Serial Port
80 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020081#define CONFIG_CONS_INDEX 1 /* Use UART0 */
82#define CONFIG_SYS_NS16550
83#define CONFIG_SYS_NS16550_SERIAL
84#define CONFIG_SYS_NS16550_REG_SIZE 1
85#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Heiko Schocherca43ba12007-01-11 15:44:44 +010086#define CONFIG_SERIAL_MULTI
Heiko Schocherca43ba12007-01-11 15:44:44 +010087
88/*
89 * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
90 */
91#define CONFIG_SYS_CLK_FREQ 33333333
92
93/*
94 * define CONFIG_BAUDRATE to the baudrate value you want to use as default
95 */
96#define CONFIG_BAUDRATE 115200
Wolfgang Denkf11033e2007-01-15 13:41:04 +010097#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
Heiko Schocherca43ba12007-01-11 15:44:44 +010098
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +010099#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100100 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100101 "echo"
102
103#undef CONFIG_BOOTARGS
104
105#define CONFIG_EXTRA_ENV_SETTINGS \
106 "netdev=eth0\0" \
107 "nfsargs=setenv bootargs root=/dev/nfs rw " \
108 "nfsroot=${serverip}:${rootpath}\0" \
109 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Heiko Schochercb482072007-01-18 11:28:51 +0100110 "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \
111 "rootfstype=jffs2\0" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100112 "addip=setenv bootargs ${bootargs} " \
113 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
114 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100115 "addcons=setenv bootargs ${bootargs} " \
116 "console=ttyS0,${baudrate}\0" \
117 "flash_nfs=run nfsargs addip addcons;" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100118 "bootm ${kernel_addr}\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100119 "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \
120 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
121 "bootm\0" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100122 "rootpath=/opt/eldk/ppc_4xx\0" \
123 "bootfile=/tftpboot/sc3/uImage\0" \
Heiko Schocherd0b6e142007-01-19 18:05:26 +0100124 "u-boot=/tftpboot/sc3/u-boot.bin\0" \
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200125 "setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100126 "kernel_addr=FFE08000\0" \
127 ""
128#undef CONFIG_BOOTCOMMAND
129
Heiko Schocherca43ba12007-01-11 15:44:44 +0100130#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100132
133#if 1 /* feel free to disable for development */
134#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200135#define CONFIG_AUTOBOOT_PROMPT \
136 "\nSC3 - booting... stop with ENTER\n"
Wolfgang Denk9045f332007-06-08 10:24:58 +0200137#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */
138#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100139#endif
140
141/*
142 * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
143 * the CONFIG_BOOTDELAY delay to boot your machine
144 */
145#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
146
147/*
148 * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
149 * set different values at the u-boot prompt
150 */
151#ifdef USE_VGA_GRAPHICS
152 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
153#else
154 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
155#endif
156/*
157 * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
158 * This reserves memory bank #4 for this purpose
159 */
160#undef CONFIG_ISP1161_PRESENT
161
162#undef CONFIG_LOADS_ECHO /* no echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100164
165#define CONFIG_NET_MULTI
166/* #define CONFIG_EEPRO100_SROM_WRITE */
167/* #define CONFIG_SHOW_MAC */
168#define CONFIG_EEPRO100
Ben Warren96e21f82008-10-27 23:50:15 -0700169
170#define CONFIG_PPC4xx_EMAC
Heiko Schocherca43ba12007-01-11 15:44:44 +0100171#define CONFIG_MII 1 /* add 405GP MII PHY management */
172#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
173
Jon Loeliger46da1e92007-07-04 22:33:30 -0500174/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500175 * BOOTP options
176 */
177#define CONFIG_BOOTP_BOOTFILESIZE
178#define CONFIG_BOOTP_BOOTPATH
179#define CONFIG_BOOTP_GATEWAY
180#define CONFIG_BOOTP_HOSTNAME
181
182
183/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500184 * Command line configuration.
185 */
186#include <config_cmd_default.h>
Heiko Schocherca43ba12007-01-11 15:44:44 +0100187
Jon Loeliger46da1e92007-07-04 22:33:30 -0500188
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200189#define CONFIG_CMD_CACHE
Jon Loeliger46da1e92007-07-04 22:33:30 -0500190#define CONFIG_CMD_DATE
191#define CONFIG_CMD_DHCP
Jon Loeliger46da1e92007-07-04 22:33:30 -0500192#define CONFIG_CMD_ELF
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200193#define CONFIG_CMD_I2C
194#define CONFIG_CMD_IDE
195#define CONFIG_CMD_IRQ
196#define CONFIG_CMD_JFFS2
197#define CONFIG_CMD_MII
198#define CONFIG_CMD_NAND
199#define CONFIG_CMD_NET
200#define CONFIG_CMD_PCI
201#define CONFIG_CMD_PING
202#define CONFIG_CMD_SOURCE
Jon Loeliger46da1e92007-07-04 22:33:30 -0500203
Heiko Schocherca43ba12007-01-11 15:44:44 +0100204
205#undef CONFIG_WATCHDOG /* watchdog disabled */
206
207/*
208 * Miscellaneous configurable options
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
211#define CONFIG_SYS_PROMPT "SC3> " /* Monitor Command Prompt */
212#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
217#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
220#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100221
222/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
224 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
225 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
Heiko Schocherca43ba12007-01-11 15:44:44 +0100226 * The Linux BASE_BAUD define should match this configuration.
227 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
Heiko Schocherca43ba12007-01-11 15:44:44 +0100229 * set Linux BASE_BAUD to 403200.
230 *
231 * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
232 * (see 405GP datasheet for descritpion)
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
235#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
236#define CONFIG_SYS_BASE_BAUD 921600 /* internal clock */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100237
238/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_BAUDRATE_TABLE \
Heiko Schocherca43ba12007-01-11 15:44:44 +0100240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
243#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100246
247/*-----------------------------------------------------------------------
248 * IIC stuff
249 *-----------------------------------------------------------------------
250 */
251#define CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100252#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200253#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100254
255#define I2C_INIT
256#define I2C_ACTIVE 0
257#define I2C_TRISTATE 0
258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_I2C_SPEED 100000 /* use the standard 100kHz speed */
260#define CONFIG_SYS_I2C_SLAVE 0x7F /* mask valid bits */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100261
262#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Heiko Schocherca43ba12007-01-11 15:44:44 +0100264
265/*-----------------------------------------------------------------------
266 * PCI stuff
267 *-----------------------------------------------------------------------
268 */
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100269#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
270#define PCI_HOST_FORCE 1 /* configure as pci host */
271#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100272
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100273#define CONFIG_PCI /* include pci support */
274#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
275#define CONFIG_PCI_PNP /* do pci plug-and-play */
276 /* resource configuration */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100277
278/* If you want to see, whats connected to your PCI bus */
279/* #define CONFIG_PCI_SCAN_SHOW */
280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
282#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
283#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
284#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
285#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
286#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
287#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
288#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100289
290/*-----------------------------------------------------------------------
291 * External peripheral base address
292 *-----------------------------------------------------------------------
293 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500294#if !defined(CONFIG_CMD_IDE)
Heiko Schocherca43ba12007-01-11 15:44:44 +0100295
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100296#undef CONFIG_IDE_LED /* no led for ide supported */
297#undef CONFIG_IDE_RESET /* no reset for ide supported */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100298
299/*-----------------------------------------------------------------------
300 * IDE/ATA stuff
301 *-----------------------------------------------------------------------
302 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500303#else
Heiko Schocherca43ba12007-01-11 15:44:44 +0100304#define CONFIG_START_IDE 1 /* check, if use IDE */
305
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100306#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
307#undef CONFIG_IDE_LED /* no led for ide supported */
308#undef CONFIG_IDE_RESET /* no reset for ide supported */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100309
310#define CONFIG_ATAPI
311#define CONFIG_DOS_PARTITION
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100313
314#ifndef IDE_USES_ISA_EMULATION
315
316/* New and faster access */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100318
319/* How many IDE busses are available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_IDE_MAXBUS 1
Heiko Schocherca43ba12007-01-11 15:44:44 +0100321
322/* What IDE ports are available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_ATA_IDE0_OFFSET 0x000 /* first is available */
324#undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100325
326/* access to the data port is calculated:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
328#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100329
330/* access to the registers is calculated:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
332#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100333
334/* access to the alternate register is calculated:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
336#define CONFIG_SYS_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100337
338#else /* IDE_USES_ISA_EMULATION */
339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100341
342/* How many IDE busses are available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_IDE_MAXBUS 1
Heiko Schocherca43ba12007-01-11 15:44:44 +0100344
345/* What IDE ports are available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* first is available */
347#undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100348
349/* access to the data port is calculated:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
351#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100352
353/* access to the registers is calculated:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
355#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100356
357/* access to the alternate register is calculated:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
359#define CONFIG_SYS_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100360
361#endif /* IDE_USES_ISA_EMULATION */
362
Jon Loeliger46da1e92007-07-04 22:33:30 -0500363#endif
Heiko Schocherca43ba12007-01-11 15:44:44 +0100364
365/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
367#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
368#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
Heiko Schocherca43ba12007-01-11 15:44:44 +0100369*/
370
371/*-----------------------------------------------------------------------
372 * Start addresses for the final memory configuration
373 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocherca43ba12007-01-11 15:44:44 +0100375 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376 * CONFIG_SYS_FLASH_BASE -> start address of internal flash
377 * CONFIG_SYS_MONITOR_BASE -> start of u-boot
Heiko Schocherca43ba12007-01-11 15:44:44 +0100378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_SDRAM_BASE 0x00000000
380#define CONFIG_SYS_FLASH_BASE 0xFFE00000
Heiko Schocher5bea7e62010-07-27 07:07:24 +0200381
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200382#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
Heiko Schocher5bea7e62010-07-27 07:07:24 +0200383#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100385
386/*
387 * For booting Linux, the board info and command line data
388 * have to be in the first 8 MiB of memory, since this is
389 * the maximum mapped by the Linux kernel during initialization.
390 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100392/*-----------------------------------------------------------------------
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100393 * FLASH organization ## FIXME: lookup in datasheet
Heiko Schocherca43ba12007-01-11 15:44:44 +0100394 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
396#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200399#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
401#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
402#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
403#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
404#define CONFIG_SYS_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100405
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200406#define CONFIG_ENV_IS_IN_FLASH 1
407#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200408#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
409#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
410#define CONFIG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
Wolfgang Denk6d3e0102007-01-16 18:30:50 +0100411
412/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200413#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
414#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Wolfgang Denk6d3e0102007-01-16 18:30:50 +0100415
Heiko Schocherca43ba12007-01-11 15:44:44 +0100416#endif
417/* let us changing anything in our environment */
418#define CONFIG_ENV_OVERWRITE
419
420/*
421 * NAND-FLASH stuff
422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_NAND_BASE 0x77D00000
Heiko Schocherca43ba12007-01-11 15:44:44 +0100425
Heiko Schochercb482072007-01-18 11:28:51 +0100426#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
427
Wolfgang Denk51056dd2007-04-11 17:22:55 +0200428/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100429#undef CONFIG_CMD_MTDPARTS
Heiko Schochercb482072007-01-18 11:28:51 +0100430#define CONFIG_JFFS2_DEV "nand0"
Wolfgang Denk51056dd2007-04-11 17:22:55 +0200431#define CONFIG_JFFS2_PART_SIZE 0x01000000
432#define CONFIG_JFFS2_PART_OFFSET 0x00000000
Heiko Schochercb482072007-01-18 11:28:51 +0100433
Heiko Schocherca43ba12007-01-11 15:44:44 +0100434/*
435 * Init Memory Controller:
436 *
437 */
438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
Heiko Schocherca43ba12007-01-11 15:44:44 +0100440#define FLASH_BASE1_PRELIM 0
441
442/*-----------------------------------------------------------------------
443 * Some informations about the internal SRAM (OCM=On Chip Memory)
444 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445 * CONFIG_SYS_OCM_DATA_ADDR -> location
446 * CONFIG_SYS_OCM_DATA_SIZE -> size
Heiko Schocherca43ba12007-01-11 15:44:44 +0100447*/
448
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_TEMP_STACK_OCM 1
450#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
451#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
Heiko Schocherca43ba12007-01-11 15:44:44 +0100452
453/*-----------------------------------------------------------------------
454 * Definitions for initial stack pointer and data area (in DPRAM):
455 * - we are using the internal 4k SRAM, so we don't need data cache mapping
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456 * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100457 * - Stackpointer will be located to
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458 * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
Stefan Roesea47a12b2010-04-15 16:07:28 +0200459 * in arch/powerpc/cpu/ppc4xx/start.S
Heiko Schocherca43ba12007-01-11 15:44:44 +0100460 */
461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#undef CONFIG_SYS_INIT_DCACHE_CS
Heiko Schocherca43ba12007-01-11 15:44:44 +0100463/* Where the internal SRAM starts */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100465/* Where the internal SRAM ends (only offset) */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200466#define CONFIG_SYS_INIT_RAM_SIZE 0x0F00
Heiko Schocherca43ba12007-01-11 15:44:44 +0100467
468/*
469
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470 CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100471 | |
472 | ^ |
473 | | |
474 | | Stack |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475 CONFIG_SYS_GBL_DATA_OFFSET ----> ------------
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100476 | |
477 | 64 Bytes |
478 | |
Wolfgang Denk553f0982010-10-26 13:32:32 +0200479 CONFIG_SYS_INIT_RAM_SIZE ------> ------------ higher address
Heiko Schocherca43ba12007-01-11 15:44:44 +0100480 (offset only)
481
482*/
483/* size in bytes reserved for initial data */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200484#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Heiko Schocherca43ba12007-01-11 15:44:44 +0100485/* Initial value of the stack pointern in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocherca43ba12007-01-11 15:44:44 +0100487
Heiko Schocherca43ba12007-01-11 15:44:44 +0100488/* ################################################################################### */
Stefan Roesea47a12b2010-04-15 16:07:28 +0200489/* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100490/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
491
492/* This chip select accesses the boot device */
493/* It depends on boot select switch if this device is 16 or 8 bit */
494
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#undef CONFIG_SYS_EBC_PB0AP
496#undef CONFIG_SYS_EBC_PB0CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100497
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#undef CONFIG_SYS_EBC_PB1AP
499#undef CONFIG_SYS_EBC_PB1CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100500
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#undef CONFIG_SYS_EBC_PB2AP
502#undef CONFIG_SYS_EBC_PB2CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100503
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#undef CONFIG_SYS_EBC_PB3AP
505#undef CONFIG_SYS_EBC_PB3CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100506
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#undef CONFIG_SYS_EBC_PB4AP
508#undef CONFIG_SYS_EBC_PB4CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100509
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#undef CONFIG_SYS_EBC_PB5AP
511#undef CONFIG_SYS_EBC_PB5CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100512
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#undef CONFIG_SYS_EBC_PB6AP
514#undef CONFIG_SYS_EBC_PB6CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100515
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#undef CONFIG_SYS_EBC_PB7AP
517#undef CONFIG_SYS_EBC_PB7CR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100518
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_EBC_CFG 0xb84ef000
Heiko Schochercb482072007-01-18 11:28:51 +0100520
Wolfgang Denkee8028b2010-11-21 20:55:42 +0100521#undef CONFIG_SDRAM_BANK0 /* use private SDRAM initialization */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100522#undef CONFIG_SPD_EEPROM
523
524/*
525 * Define this to get more information about system configuration
526 */
527/* #define SC3_DEBUGOUT */
528#undef SC3_DEBUGOUT
529
530/***********************************************************************
531 * External peripheral base address
532 ***********************************************************************/
533
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000
Heiko Schocherca43ba12007-01-11 15:44:44 +0100535/*
536 Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
537 Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
538 das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
539 auf ISA- und PCI-Zyklen)
540 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
542/*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0x79000000 */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100543
544/************************************************************
545 * Video support
546 ************************************************************/
547
548#ifdef USE_VGA_GRAPHICS
549#define CONFIG_VIDEO /* To enable video controller support */
550#define CONFIG_VIDEO_CT69000
551#define CONFIG_CFB_CONSOLE
552/* #define CONFIG_VIDEO_LOGO */
553#define CONFIG_VGA_AS_SINGLE_DEVICE
554#define CONFIG_VIDEO_SW_CURSOR
555/* #define CONFIG_VIDEO_HW_CURSOR */
556#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
557
558#define VIDEO_HW_RECTFILL
559#define VIDEO_HW_BITBLT
560
561#endif
562
563/************************************************************
564 * Ident
565 ************************************************************/
566#define CONFIG_SC3_VERSION "r1.4"
567
568#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
569
570#endif /* __CONFIG_H */