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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bin Meng9c7dea62015-05-25 22:35:04 +08002/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng9c7dea62015-05-25 22:35:04 +08004 */
5
6#ifndef _ARCH_IRQ_H_
7#define _ARCH_IRQ_H_
8
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11/**
12 * Intel interrupt router configuration mechanism
13 *
14 * There are two known ways of Intel interrupt router configuration mechanism
15 * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
16 * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
17 * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
18 * in the IBASE register block where IBASE is memory-mapped.
19 */
20enum pirq_config {
21 PIRQ_VIA_PCI,
22 PIRQ_VIA_IBASE
23};
24
25/**
26 * Intel interrupt router control block
27 *
28 * Its members' value will be filled in based on device tree's input.
29 *
30 * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
31 * @link_base: link value base number
Bin Mengdcec5d52018-06-12 01:26:45 -070032 * @link_num: number of PIRQ links supported
Bin Meng9c7dea62015-05-25 22:35:04 +080033 * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
34 * IRQ N is available to be routed
35 * @lb_bdf: irq router's PCI bus/device/function number encoding
36 * @ibase: IBASE register block base address
Bin Mengd4e61f52016-05-07 07:46:14 -070037 * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
38 * @actl_addr: ACTL register offset
Bin Meng9c7dea62015-05-25 22:35:04 +080039 */
40struct irq_router {
41 int config;
42 u32 link_base;
Bin Mengdcec5d52018-06-12 01:26:45 -070043 int link_num;
Bin Meng9c7dea62015-05-25 22:35:04 +080044 u16 irq_mask;
45 u32 bdf;
46 u32 ibase;
Bin Mengd4e61f52016-05-07 07:46:14 -070047 bool actl_8bit;
48 int actl_addr;
Bin Meng9c7dea62015-05-25 22:35:04 +080049};
50
51struct pirq_routing {
52 int bdf;
53 int pin;
54 int pirq;
55};
56
Bin Meng594d0892018-06-03 19:04:23 -070057/**
58 * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number
59 *
60 * @reg: PIRQ routing register offset from the base address
61 * @base: PIRQ routing register block base address
62 * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
63 */
64static inline int pirq_reg_to_linkno(int reg, int base)
65{
66 return reg - base;
67}
68
69/**
70 * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset
71 *
72 * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
73 * @base: PIRQ routing register block base address
74 * @return: PIRQ routing register offset from the base address
75 */
76static inline int pirq_linkno_to_reg(int linkno, int base)
77{
78 return linkno + base;
79}
Bin Meng9c7dea62015-05-25 22:35:04 +080080
81#define PIRQ_BITMAP 0xdef8
82
Bin Meng9c7dea62015-05-25 22:35:04 +080083#endif /* _ARCH_IRQ_H_ */