Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _ARCH_IRQ_H_ |
| 7 | #define _ARCH_IRQ_H_ |
| 8 | |
| 9 | #include <dt-bindings/interrupt-router/intel-irq.h> |
| 10 | |
| 11 | /** |
| 12 | * Intel interrupt router configuration mechanism |
| 13 | * |
| 14 | * There are two known ways of Intel interrupt router configuration mechanism |
| 15 | * so far. On most cases, the IRQ routing configuraiton is controlled by PCI |
| 16 | * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). |
| 17 | * On some newer platforms like BayTrail and Braswell, the IRQ routing is now |
| 18 | * in the IBASE register block where IBASE is memory-mapped. |
| 19 | */ |
| 20 | enum pirq_config { |
| 21 | PIRQ_VIA_PCI, |
| 22 | PIRQ_VIA_IBASE |
| 23 | }; |
| 24 | |
| 25 | /** |
| 26 | * Intel interrupt router control block |
| 27 | * |
| 28 | * Its members' value will be filled in based on device tree's input. |
| 29 | * |
| 30 | * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE |
| 31 | * @link_base: link value base number |
Bin Meng | dcec5d5 | 2018-06-12 01:26:45 -0700 | [diff] [blame^] | 32 | * @link_num: number of PIRQ links supported |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 33 | * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means |
| 34 | * IRQ N is available to be routed |
| 35 | * @lb_bdf: irq router's PCI bus/device/function number encoding |
| 36 | * @ibase: IBASE register block base address |
Bin Meng | d4e61f5 | 2016-05-07 07:46:14 -0700 | [diff] [blame] | 37 | * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset) |
| 38 | * @actl_addr: ACTL register offset |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 39 | */ |
| 40 | struct irq_router { |
| 41 | int config; |
| 42 | u32 link_base; |
Bin Meng | dcec5d5 | 2018-06-12 01:26:45 -0700 | [diff] [blame^] | 43 | int link_num; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 44 | u16 irq_mask; |
| 45 | u32 bdf; |
| 46 | u32 ibase; |
Bin Meng | d4e61f5 | 2016-05-07 07:46:14 -0700 | [diff] [blame] | 47 | bool actl_8bit; |
| 48 | int actl_addr; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | struct pirq_routing { |
| 52 | int bdf; |
| 53 | int pin; |
| 54 | int pirq; |
| 55 | }; |
| 56 | |
Bin Meng | 594d089 | 2018-06-03 19:04:23 -0700 | [diff] [blame] | 57 | /** |
| 58 | * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number |
| 59 | * |
| 60 | * @reg: PIRQ routing register offset from the base address |
| 61 | * @base: PIRQ routing register block base address |
| 62 | * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) |
| 63 | */ |
| 64 | static inline int pirq_reg_to_linkno(int reg, int base) |
| 65 | { |
| 66 | return reg - base; |
| 67 | } |
| 68 | |
| 69 | /** |
| 70 | * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset |
| 71 | * |
| 72 | * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) |
| 73 | * @base: PIRQ routing register block base address |
| 74 | * @return: PIRQ routing register offset from the base address |
| 75 | */ |
| 76 | static inline int pirq_linkno_to_reg(int linkno, int base) |
| 77 | { |
| 78 | return linkno + base; |
| 79 | } |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 80 | |
| 81 | #define PIRQ_BITMAP 0xdef8 |
| 82 | |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 83 | #endif /* _ARCH_IRQ_H_ */ |