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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
4 *
5 * Configuration for the Cogent CSB226 board. For details see
6 * http://www.cogcomp.com/csb_csb226.htm
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * include/configs/csb226.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
wdenk699b13a2002-11-03 18:03:52 +000034#define DEBUG 1
35
wdenkfe8c2802002-11-03 00:38:21 +000036/*
wdenkfe8c2802002-11-03 00:38:21 +000037 * High Level Configuration Options
38 * (easy to change)
39 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020040#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
wdenkfe8c2802002-11-03 00:38:21 +000041#define CONFIG_CSB226 1 /* on a CSB226 board */
42
43#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44 /* for timer/console/ethernet */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020045
46/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000047#define CONFIG_SYS_DCACHE_OFF
Marek Vasut38f8eb32010-10-20 20:43:41 +020048#define CONFIG_SYS_TEXT_BASE 0x0
wdenkfe8c2802002-11-03 00:38:21 +000049/*
50 * Hardware drivers
51 */
52
53/*
54 * select serial console configuration
55 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020056#define CONFIG_PXA_SERIAL
wdenk47cd00f2003-03-06 13:39:27 +000057#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
wdenkfe8c2802002-11-03 00:38:21 +000058
59/* allow to overwrite serial and ethaddr */
60#define CONFIG_ENV_OVERWRITE
61
62#define CONFIG_BAUDRATE 19200
wdenk47cd00f2003-03-06 13:39:27 +000063#undef CONFIG_MISC_INIT_R /* not used yet */
wdenkfe8c2802002-11-03 00:38:21 +000064
wdenkfe8c2802002-11-03 00:38:21 +000065
Jon Loeliger37e4f242007-07-04 22:31:56 -050066/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050067 * BOOTP options
68 */
69#define CONFIG_BOOTP_BOOTFILESIZE
70#define CONFIG_BOOTP_BOOTPATH
71#define CONFIG_BOOTP_GATEWAY
72#define CONFIG_BOOTP_HOSTNAME
73
74
75/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050076 * Command line configuration.
77 */
78#include <config_cmd_default.h>
79
80#define CONFIG_CMD_BDI
81#define CONFIG_CMD_LOADB
82#define CONFIG_CMD_IMI
83#define CONFIG_CMD_FLASH
84#define CONFIG_CMD_MEMORY
85#define CONFIG_CMD_NET
Mike Frysingerbdab39d2009-01-28 19:08:14 -050086#define CONFIG_CMD_SAVEENV
Jon Loeliger37e4f242007-07-04 22:31:56 -050087#define CONFIG_CMD_RUN
88#define CONFIG_CMD_ASKENV
89#define CONFIG_CMD_ECHO
90#define CONFIG_CMD_DHCP
91#define CONFIG_CMD_CACHE
92
wdenkfe8c2802002-11-03 00:38:21 +000093
wdenk699b13a2002-11-03 18:03:52 +000094#define CONFIG_BOOTDELAY 3
wdenk993cad92003-06-26 22:04:09 +000095#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
wdenkfe8c2802002-11-03 00:38:21 +000096#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
97#define CONFIG_NETMASK 255.255.255.0
98#define CONFIG_IPADDR 192.168.1.56
wdenk993cad92003-06-26 22:04:09 +000099#define CONFIG_SERVERIP 192.168.1.5
wdenk699b13a2002-11-03 18:03:52 +0000100#define CONFIG_BOOTCOMMAND "bootm 0x40000"
wdenk384ae022002-11-05 00:17:55 +0000101#define CONFIG_SHOW_BOOT_PROGRESS
wdenkfe8c2802002-11-03 00:38:21 +0000102
wdenk47cd00f2003-03-06 13:39:27 +0000103#define CONFIG_CMDLINE_TAG 1
104
Jon Loeliger37e4f242007-07-04 22:31:56 -0500105#if defined(CONFIG_CMD_KGDB)
wdenk47cd00f2003-03-06 13:39:27 +0000106#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
wdenkfe8c2802002-11-03 00:38:21 +0000107#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
108#endif
109
110/*
111 * Miscellaneous configurable options
112 */
113
114/*
115 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
116 * used for the RAM copy of the uboot code
117 *
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_MALLOC_LEN (128*1024)
wdenkfe8c2802002-11-03 00:38:21 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LONGHELP /* undef to save memory */
122#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
123#define CONFIG_SYS_CBSIZE 128 /* Console I/O Buffer Size */
124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
129#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkfe8c2802002-11-03 00:38:21 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
wdenkfe8c2802002-11-03 00:38:21 +0000132 /* RS: where is this documented? */
133 /* RS: is this where U-Boot is */
134 /* RS: relocated to in RAM? */
135
Micha Kalfon94a33122009-02-11 19:50:11 +0200136#define CONFIG_SYS_HZ 1000
wdenkfe8c2802002-11-03 00:38:21 +0000137 /* RS: the oscillator is actually 3680130?? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
wdenkfe8c2802002-11-03 00:38:21 +0000139 /* 0101000001 */
140 /* ^^^^^ Memory Speed 99.53 MHz */
141 /* ^^ Run Mode Speed = 2x Mem Speed */
142 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
wdenkfe8c2802002-11-03 00:38:21 +0000145
wdenk8bde7f72003-06-27 21:31:46 +0000146 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfe8c2802002-11-03 00:38:21 +0000148
149/*
wdenk993cad92003-06-26 22:04:09 +0000150 * Network chip
151 */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700152#define CONFIG_NET_MULTI
153#define CONFIG_CS8900
154#define CONFIG_CS8900_BUS32
155#define CONFIG_CS8900_BASE 0x08000000
wdenk993cad92003-06-26 22:04:09 +0000156
157/*
wdenkfe8c2802002-11-03 00:38:21 +0000158 * Stack sizes
159 *
160 * The stack sizes are set up in start.S using the settings below
161 */
162#define CONFIG_STACKSIZE (128*1024) /* regular stack */
163#ifdef CONFIG_USE_IRQ
164#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
165#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
166#endif
167
168/*
169 * Physical Memory Map
170 */
171#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
172#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
173#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
174
175#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
176#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
179#define CONFIG_SYS_DRAM_SIZE 0x02000000
wdenkfe8c2802002-11-03 00:38:21 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkfe8c2802002-11-03 00:38:21 +0000182
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200183#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200184#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200185
wdenk993cad92003-06-26 22:04:09 +0000186# if 0
187/* FIXME: switch to _documented_ registers */
188/*
189 * GPIO settings
190 *
191 * GP15 == nCS1 is 1
192 * GP24 == SFRM is 1
193 * GP25 == TXD is 1
194 * GP33 == nCS5 is 1
195 * GP39 == FFTXD is 1
196 * GP41 == RTS is 1
197 * GP47 == TXD is 1
198 * GP49 == nPWE is 1
199 * GP62 == LED_B is 1
200 * GP63 == TDM_OE is 1
201 * GP78 == nCS2 is 1
202 * GP79 == nCS3 is 1
203 * GP80 == nCS4 is 1
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_GPSR0_VAL 0x03008000
206#define CONFIG_SYS_GPSR1_VAL 0xC0028282
207#define CONFIG_SYS_GPSR2_VAL 0x0001C000
wdenk993cad92003-06-26 22:04:09 +0000208
209/* GP02 == DON_RST is 0
210 * GP23 == SCLK is 0
211 * GP45 == USB_ACT is 0
212 * GP60 == PLLEN is 0
213 * GP61 == LED_A is 0
214 * GP73 == SWUPD_LED is 0
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_GPCR0_VAL 0x00800004
217#define CONFIG_SYS_GPCR1_VAL 0x30002000
218#define CONFIG_SYS_GPCR2_VAL 0x00000100
wdenk993cad92003-06-26 22:04:09 +0000219
220/* GP00 == DON_READY is input
221 * GP01 == DON_OK is input
222 * GP02 == DON_RST is output
223 * GP03 == RESET_IND is input
224 * GP07 == RES11 is input
225 * GP09 == RES12 is input
226 * GP11 == SWUPDATE is input
227 * GP14 == nPOWEROK is input
228 * GP15 == nCS1 is output
229 * GP17 == RES22 is input
230 * GP18 == RDY is input
231 * GP23 == SCLK is output
232 * GP24 == SFRM is output
233 * GP25 == TXD is output
234 * GP26 == RXD is input
235 * GP32 == RES21 is input
236 * GP33 == nCS5 is output
237 * GP34 == FFRXD is input
238 * GP35 == CTS is input
239 * GP39 == FFTXD is output
240 * GP41 == RTS is output
241 * GP42 == USB_OK is input
242 * GP45 == USB_ACT is output
243 * GP46 == RXD is input
244 * GP47 == TXD is output
245 * GP49 == nPWE is output
246 * GP58 == nCPUBUSINT is input
247 * GP59 == LANINT is input
248 * GP60 == PLLEN is output
249 * GP61 == LED_A is output
250 * GP62 == LED_B is output
251 * GP63 == TDM_OE is output
252 * GP64 == nDSPINT is input
253 * GP65 == STRAP0 is input
254 * GP67 == STRAP1 is input
255 * GP69 == STRAP2 is input
256 * GP70 == STRAP3 is input
257 * GP71 == STRAP4 is input
258 * GP73 == SWUPD_LED is output
259 * GP78 == nCS2 is output
260 * GP79 == nCS3 is output
261 * GP80 == nCS4 is output
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_GPDR0_VAL 0x03808004
264#define CONFIG_SYS_GPDR1_VAL 0xF002A282
265#define CONFIG_SYS_GPDR2_VAL 0x0001C200
wdenk993cad92003-06-26 22:04:09 +0000266
267/* GP15 == nCS1 is AF10
268 * GP18 == RDY is AF01
269 * GP23 == SCLK is AF10
270 * GP24 == SFRM is AF10
271 * GP25 == TXD is AF10
272 * GP26 == RXD is AF01
273 * GP33 == nCS5 is AF10
274 * GP34 == FFRXD is AF01
275 * GP35 == CTS is AF01
276 * GP39 == FFTXD is AF10
277 * GP41 == RTS is AF10
278 * GP46 == RXD is AF10
279 * GP47 == TXD is AF01
280 * GP49 == nPWE is AF10
281 * GP78 == nCS2 is AF10
282 * GP79 == nCS3 is AF10
283 * GP80 == nCS4 is AF10
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
286#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
287#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
288#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
289#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
290#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenk993cad92003-06-26 22:04:09 +0000291
292
293/* FIXME: set GPIO_RER/FER */
294
295/* RDH = 1
296 * PH = 1
297 * VFS = 1
298 * BFS = 1
299 * SSS = 1
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_PSSR_VAL 0x37
wdenk993cad92003-06-26 22:04:09 +0000302
303/*
304 * Memory settings
305 *
306 * This is the configuration for nCS0/1 -> flash banks
307 * configuration for nCS1:
308 * [31] 0 - Slower Device
309 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
310 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
311 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
312 * [19] 1 - 16 Bit bus width
313 * [18:16] 000 - nonburst RAM or FLASH
314 * configuration for nCS0:
315 * [15] 0 - Slower Device
316 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
317 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
318 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
319 * [03] 1 - 16 Bit bus width
320 * [02:00] 000 - nonburst RAM or FLASH
321 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
wdenk993cad92003-06-26 22:04:09 +0000323
324/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
325 * configuration for nCS3: DSP
326 * [31] 0 - Slower Device
327 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
328 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
329 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
330 * [19] 1 - 16 Bit bus width
331 * [18:16] 100 - variable latency I/O
332 * configuration for nCS2: TDM-Switch
333 * [15] 0 - Slower Device
334 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
335 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
336 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
337 * [03] 1 - 16 Bit bus width
338 * [02:00] 100 - variable latency I/O
339 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
wdenk993cad92003-06-26 22:04:09 +0000341
342/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
343 *
344 * configuration for nCS5: LAN Controller
345 * [31] 0 - Slower Device
346 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
347 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
348 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
349 * [19] 1 - 16 Bit bus width
350 * [18:16] 100 - variable latency I/O
351 * configuration for nCS4: ExtBus
352 * [15] 0 - Slower Device
353 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
354 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
355 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
356 * [03] 1 - 16 Bit bus width
357 * [02:00] 100 - variable latency I/O
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
wdenk993cad92003-06-26 22:04:09 +0000360
361/* MDCNFG: SDRAM Configuration Register
362 *
363 * [31:29] 000 - reserved
364 * [28] 0 - no SA1111 compatiblity mode
365 * [27] 0 - latch return data with return clock
366 * [26] 0 - alternate addressing for pair 2/3
367 * [25:24] 00 - timings
368 * [23] 0 - internal banks in lower partition 2/3 (not used)
369 * [22:21] 00 - row address bits for partition 2/3 (not used)
370 * [20:19] 00 - column address bits for partition 2/3 (not used)
371 * [18] 0 - SDRAM partition 2/3 width is 32 bit
372 * [17] 0 - SDRAM partition 3 disabled
373 * [16] 0 - SDRAM partition 2 disabled
374 * [15:13] 000 - reserved
375 * [12] 1 - SA1111 compatiblity mode
376 * [11] 1 - latch return data with return clock
377 * [10] 0 - no alternate addressing for pair 0/1
378 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
379 * [7] 1 - 4 internal banks in lower partition pair
380 * [06:05] 10 - 13 row address bits for partition 0/1
381 * [04:03] 01 - 9 column address bits for partition 0/1
382 * [02] 0 - SDRAM partition 0/1 width is 32 bit
383 * [01] 0 - disable SDRAM partition 1
384 * [00] 1 - enable SDRAM partition 0
385 */
386/* use the configuration above but disable partition 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
wdenk993cad92003-06-26 22:04:09 +0000388
389/* MDREFR: SDRAM Refresh Control Register
390 *
391 * [32:26] 0 - reserved
392 * [25] 0 - K2FREE: not free running
393 * [24] 0 - K1FREE: not free running
394 * [23] 1 - K0FREE: not free running
395 * [22] 0 - SLFRSH: self refresh disabled
396 * [21] 0 - reserved
397 * [20] 0 - APD: no auto power down
398 * [19] 0 - K2DB2: SDCLK2 is MemClk
399 * [18] 0 - K2RUN: disable SDCLK2
400 * [17] 0 - K1DB2: SDCLK1 is MemClk
401 * [16] 1 - K1RUN: enable SDCLK1
402 * [15] 1 - E1PIN: SDRAM clock enable
403 * [14] 1 - K0DB2: SDCLK0 is MemClk
404 * [13] 0 - K0RUN: disable SDCLK0
405 * [12] 1 - E0PIN: disable SDCKE0
406 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
407 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_MDREFR_VAL 0x0081D018
wdenk993cad92003-06-26 22:04:09 +0000409
410/* MDMRS: Mode Register Set Configuration Register
411 *
412 * [31] 0 - reserved
413 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
414 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
415 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
416 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
417 * [15] 0 - reserved
418 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
419 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
420 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
421 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_MDMRS_VAL 0x00020022
wdenk993cad92003-06-26 22:04:09 +0000424
425/*
426 * PCMCIA and CF Interfaces
427 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_MECR_VAL 0x00000000
429#define CONFIG_SYS_MCMEM0_VAL 0x00000000
430#define CONFIG_SYS_MCMEM1_VAL 0x00000000
431#define CONFIG_SYS_MCATT0_VAL 0x00000000
432#define CONFIG_SYS_MCATT1_VAL 0x00000000
433#define CONFIG_SYS_MCIO0_VAL 0x00000000
434#define CONFIG_SYS_MCIO1_VAL 0x00000000
wdenk993cad92003-06-26 22:04:09 +0000435#endif
436
wdenkfe8c2802002-11-03 00:38:21 +0000437/*
438 * GPIO settings
439 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_GPSR0_VAL 0xFFFFFFFF
441#define CONFIG_SYS_GPSR1_VAL 0xFFFFFFFF
442#define CONFIG_SYS_GPSR2_VAL 0xFFFFFFFF
443#define CONFIG_SYS_GPCR0_VAL 0x08022080
444#define CONFIG_SYS_GPCR1_VAL 0x00000000
445#define CONFIG_SYS_GPCR2_VAL 0x00000000
446#define CONFIG_SYS_GPDR0_VAL 0xCD82A878
447#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB80
448#define CONFIG_SYS_GPDR2_VAL 0x0001FFFF
449#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
450#define CONFIG_SYS_GAFR0_U_VAL 0xA5254010
451#define CONFIG_SYS_GAFR1_L_VAL 0x599A9550
452#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
453#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
454#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkfe8c2802002-11-03 00:38:21 +0000455
456/* FIXME: set GPIO_RER/FER */
457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_PSSR_VAL 0x20
wdenkfe8c2802002-11-03 00:38:21 +0000459
Marek Vasuteb0e11b2010-10-20 20:17:51 +0200460#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
461#define CONFIG_SYS_CKEN 0x0
462
wdenkfe8c2802002-11-03 00:38:21 +0000463/*
464 * Memory settings
465 */
wdenk993cad92003-06-26 22:04:09 +0000466
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_MSC0_VAL 0x2ef15af0
468#define CONFIG_SYS_MSC1_VAL 0x00003ff4
469#define CONFIG_SYS_MSC2_VAL 0x7ff07ff0
470#define CONFIG_SYS_MDCNFG_VAL 0x09a909a9
471#define CONFIG_SYS_MDREFR_VAL 0x038ff030
472#define CONFIG_SYS_MDMRS_VAL 0x00220022
Marek Vasut38f8eb32010-10-20 20:43:41 +0200473#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
474#define CONFIG_SYS_SXCNFG_VAL 0x00000000
wdenkfe8c2802002-11-03 00:38:21 +0000475
476/*
477 * PCMCIA and CF Interfaces
478 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_MECR_VAL 0x00000000
480#define CONFIG_SYS_MCMEM0_VAL 0x00000000
481#define CONFIG_SYS_MCMEM1_VAL 0x00000000
482#define CONFIG_SYS_MCATT0_VAL 0x00000000
483#define CONFIG_SYS_MCATT1_VAL 0x00000000
484#define CONFIG_SYS_MCIO0_VAL 0x00000000
485#define CONFIG_SYS_MCIO1_VAL 0x00000000
wdenkfe8c2802002-11-03 00:38:21 +0000486
wdenk384ae022002-11-05 00:17:55 +0000487#define CSB226_USER_LED0 0x00000008
488#define CSB226_USER_LED1 0x00000010
489#define CSB226_USER_LED2 0x00000020
490
wdenkfe8c2802002-11-03 00:38:21 +0000491
492/*
493 * FLASH and environment organization
494 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
496#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
wdenkfe8c2802002-11-03 00:38:21 +0000497
498/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
500#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkfe8c2802002-11-03 00:38:21 +0000501
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200502#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200503#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
wdenkfe8c2802002-11-03 00:38:21 +0000504 /* Addr of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200505#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkfe8c2802002-11-03 00:38:21 +0000506
507#endif /* __CONFIG_H */