Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * ASPEED FMC/SPI Controller driver |
| 4 | * |
| 5 | * Copyright (c) 2022 ASPEED Corporation. |
| 6 | * Copyright (c) 2022 IBM Corporation. |
| 7 | * |
| 8 | * Author: |
| 9 | * Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
| 10 | * Cedric Le Goater <clg@kaod.org> |
| 11 | */ |
| 12 | |
| 13 | #include <asm/io.h> |
| 14 | #include <clk.h> |
| 15 | #include <common.h> |
| 16 | #include <dm.h> |
| 17 | #include <dm/device_compat.h> |
| 18 | #include <linux/bitops.h> |
| 19 | #include <linux/bug.h> |
| 20 | #include <linux/err.h> |
| 21 | #include <linux/iopoll.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/mtd/spi-nor.h> |
| 24 | #include <linux/sizes.h> |
| 25 | #include <malloc.h> |
| 26 | #include <spi.h> |
| 27 | #include <spi-mem.h> |
| 28 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 29 | #define ASPEED_SPI_MAX_CS 5 |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 30 | |
| 31 | #define CTRL_IO_SINGLE_DATA 0 |
| 32 | #define CTRL_IO_QUAD_DATA BIT(30) |
| 33 | #define CTRL_IO_DUAL_DATA BIT(29) |
| 34 | |
| 35 | #define CTRL_IO_MODE_USER GENMASK(1, 0) |
| 36 | #define CTRL_IO_MODE_CMD_READ BIT(0) |
| 37 | #define CTRL_IO_MODE_CMD_WRITE BIT(1) |
| 38 | #define CTRL_STOP_ACTIVE BIT(2) |
| 39 | |
| 40 | struct aspeed_spi_regs { |
| 41 | u32 conf; /* 0x00 CE Type Setting */ |
| 42 | u32 ctrl; /* 0x04 CE Control */ |
| 43 | u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ |
| 44 | u32 cmd_ctrl; /* 0x0c Command Control */ |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 45 | u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x20 CEx Control */ |
| 46 | u32 _reserved0[3]; /* .. */ |
| 47 | u32 segment_addr[ASPEED_SPI_MAX_CS]; /* 0x30 .. 0x40 Segment Address */ |
| 48 | u32 _reserved1[3]; /* .. */ |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 49 | u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */ |
| 50 | u32 _reserved2[11]; /* .. */ |
| 51 | u32 dma_ctrl; /* 0x80 DMA Control/Status */ |
| 52 | u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ |
| 53 | u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ |
| 54 | u32 dma_len; /* 0x8c DMA Length Register */ |
| 55 | u32 dma_checksum; /* 0x90 Checksum Calculation Result */ |
| 56 | u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */ |
| 57 | }; |
| 58 | |
| 59 | struct aspeed_spi_plat { |
| 60 | u8 max_cs; |
| 61 | void __iomem *ahb_base; /* AHB address base for all flash devices. */ |
| 62 | fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */ |
| 63 | }; |
| 64 | |
| 65 | struct aspeed_spi_flash { |
| 66 | void __iomem *ahb_base; |
| 67 | u32 ahb_decoded_sz; |
| 68 | u32 ce_ctrl_user; |
| 69 | u32 ce_ctrl_read; |
| 70 | }; |
| 71 | |
| 72 | struct aspeed_spi_priv { |
| 73 | u32 num_cs; |
| 74 | struct aspeed_spi_regs *regs; |
| 75 | struct aspeed_spi_info *info; |
| 76 | struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 77 | bool fixed_decoded_range; |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | struct aspeed_spi_info { |
| 81 | u32 io_mode_mask; |
| 82 | u32 max_bus_width; |
| 83 | u32 min_decoded_sz; |
| 84 | void (*set_4byte)(struct udevice *bus, u32 cs); |
| 85 | u32 (*segment_start)(struct udevice *bus, u32 reg); |
| 86 | u32 (*segment_end)(struct udevice *bus, u32 reg); |
| 87 | u32 (*segment_reg)(u32 start, u32 end); |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 88 | int (*adjust_decoded_sz)(struct udevice *bus); |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 89 | }; |
| 90 | |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 91 | struct aspeed_spi_decoded_range { |
| 92 | u32 cs; |
| 93 | u32 ahb_base; |
| 94 | u32 sz; |
| 95 | }; |
| 96 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 97 | static const struct aspeed_spi_info ast2400_spi_info; |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 98 | static const struct aspeed_spi_info ast2500_fmc_info; |
| 99 | static const struct aspeed_spi_info ast2500_spi_info; |
Chin-Ting Kuo | 992d02e | 2022-08-19 17:01:10 +0800 | [diff] [blame] | 100 | static int aspeed_spi_decoded_range_config(struct udevice *bus); |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 101 | static int aspeed_spi_trim_decoded_size(struct udevice *bus); |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 102 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 103 | static u32 aspeed_spi_get_io_mode(u32 bus_width) |
| 104 | { |
| 105 | switch (bus_width) { |
| 106 | case 1: |
| 107 | return CTRL_IO_SINGLE_DATA; |
| 108 | case 2: |
| 109 | return CTRL_IO_DUAL_DATA; |
| 110 | case 4: |
| 111 | return CTRL_IO_QUAD_DATA; |
| 112 | default: |
| 113 | /* keep in default value */ |
| 114 | return CTRL_IO_SINGLE_DATA; |
| 115 | } |
| 116 | } |
| 117 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 118 | static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg) |
| 119 | { |
| 120 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 121 | u32 start_offset = ((reg >> 16) & 0xff) << 23; |
| 122 | |
| 123 | if (start_offset == 0) |
| 124 | return (u32)plat->ahb_base; |
| 125 | |
| 126 | return (u32)plat->ahb_base + start_offset; |
| 127 | } |
| 128 | |
| 129 | static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg) |
| 130 | { |
| 131 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 132 | u32 end_offset = ((reg >> 24) & 0xff) << 23; |
| 133 | |
| 134 | /* Meaningless end_offset, set to physical ahb base. */ |
| 135 | if (end_offset == 0) |
| 136 | return (u32)plat->ahb_base; |
| 137 | |
| 138 | return (u32)plat->ahb_base + end_offset; |
| 139 | } |
| 140 | |
| 141 | static u32 ast2400_spi_segment_reg(u32 start, u32 end) |
| 142 | { |
| 143 | if (start == end) |
| 144 | return 0; |
| 145 | |
| 146 | return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24); |
| 147 | } |
| 148 | |
| 149 | static void ast2400_fmc_chip_set_4byte(struct udevice *bus, u32 cs) |
| 150 | { |
| 151 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 152 | u32 reg_val; |
| 153 | |
| 154 | reg_val = readl(&priv->regs->ctrl); |
| 155 | reg_val |= 0x1 << cs; |
| 156 | writel(reg_val, &priv->regs->ctrl); |
| 157 | } |
| 158 | |
| 159 | static void ast2400_spi_chip_set_4byte(struct udevice *bus, u32 cs) |
| 160 | { |
| 161 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 162 | struct aspeed_spi_flash *flash = &priv->flashes[cs]; |
| 163 | |
| 164 | flash->ce_ctrl_read |= BIT(13); |
| 165 | writel(flash->ce_ctrl_read, &priv->regs->ctrl); |
| 166 | } |
| 167 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 168 | static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg) |
| 169 | { |
| 170 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 171 | u32 start_offset = ((reg >> 16) & 0xff) << 23; |
| 172 | |
| 173 | if (start_offset == 0) |
| 174 | return (u32)plat->ahb_base; |
| 175 | |
| 176 | return (u32)plat->ahb_base + start_offset; |
| 177 | } |
| 178 | |
| 179 | static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg) |
| 180 | { |
| 181 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 182 | u32 end_offset = ((reg >> 24) & 0xff) << 23; |
| 183 | |
| 184 | /* Meaningless end_offset, set to physical ahb base. */ |
| 185 | if (end_offset == 0) |
| 186 | return (u32)plat->ahb_base; |
| 187 | |
| 188 | return (u32)plat->ahb_base + end_offset; |
| 189 | } |
| 190 | |
| 191 | static u32 ast2500_spi_segment_reg(u32 start, u32 end) |
| 192 | { |
| 193 | if (start == end) |
| 194 | return 0; |
| 195 | |
| 196 | return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24); |
| 197 | } |
| 198 | |
| 199 | static void ast2500_spi_chip_set_4byte(struct udevice *bus, u32 cs) |
| 200 | { |
| 201 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 202 | u32 reg_val; |
| 203 | |
| 204 | reg_val = readl(&priv->regs->ctrl); |
| 205 | reg_val |= 0x1 << cs; |
| 206 | writel(reg_val, &priv->regs->ctrl); |
| 207 | } |
| 208 | |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 209 | /* |
| 210 | * For AST2500, the minimum address decoded size for each CS |
| 211 | * is 8MB instead of zero. This address decoded size is |
| 212 | * mandatory for each CS no matter whether it will be used. |
| 213 | * This is a HW limitation. |
| 214 | */ |
| 215 | static int ast2500_adjust_decoded_size(struct udevice *bus) |
| 216 | { |
| 217 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 218 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 219 | struct aspeed_spi_flash *flashes = &priv->flashes[0]; |
| 220 | int ret; |
| 221 | int i; |
| 222 | int cs; |
| 223 | u32 pre_sz; |
| 224 | u32 lack_sz; |
| 225 | |
| 226 | /* Assign min_decoded_sz to unused CS. */ |
| 227 | for (cs = priv->num_cs; cs < plat->max_cs; cs++) |
| 228 | flashes[cs].ahb_decoded_sz = priv->info->min_decoded_sz; |
| 229 | |
| 230 | /* |
| 231 | * If commnad mode or normal mode is used, the start address of a |
| 232 | * decoded range should be multiple of its related flash size. |
| 233 | * Namely, the total decoded size from flash 0 to flash N should |
| 234 | * be multiple of the size of flash (N + 1). |
| 235 | */ |
| 236 | for (cs = priv->num_cs - 1; cs >= 0; cs--) { |
| 237 | pre_sz = 0; |
| 238 | for (i = 0; i < cs; i++) |
| 239 | pre_sz += flashes[i].ahb_decoded_sz; |
| 240 | |
| 241 | if (flashes[cs].ahb_decoded_sz != 0 && |
| 242 | (pre_sz % flashes[cs].ahb_decoded_sz) != 0) { |
| 243 | lack_sz = flashes[cs].ahb_decoded_sz - |
| 244 | (pre_sz % flashes[cs].ahb_decoded_sz); |
| 245 | flashes[0].ahb_decoded_sz += lack_sz; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | ret = aspeed_spi_trim_decoded_size(bus); |
| 250 | if (ret != 0) |
| 251 | return ret; |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 256 | static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg) |
| 257 | { |
| 258 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 259 | u32 start_offset = (reg << 16) & 0x0ff00000; |
| 260 | |
| 261 | if (start_offset == 0) |
| 262 | return (u32)plat->ahb_base; |
| 263 | |
| 264 | return (u32)plat->ahb_base + start_offset; |
| 265 | } |
| 266 | |
| 267 | static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg) |
| 268 | { |
| 269 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 270 | u32 end_offset = reg & 0x0ff00000; |
| 271 | |
| 272 | /* Meaningless end_offset, set to physical ahb base. */ |
| 273 | if (end_offset == 0) |
| 274 | return (u32)plat->ahb_base; |
| 275 | |
| 276 | return (u32)plat->ahb_base + end_offset + 0x100000; |
| 277 | } |
| 278 | |
| 279 | static u32 ast2600_spi_segment_reg(u32 start, u32 end) |
| 280 | { |
| 281 | if (start == end) |
| 282 | return 0; |
| 283 | |
| 284 | return ((start & 0x0ff00000) >> 16) | ((end - 0x100000) & 0x0ff00000); |
| 285 | } |
| 286 | |
| 287 | static void ast2600_spi_chip_set_4byte(struct udevice *bus, u32 cs) |
| 288 | { |
| 289 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 290 | u32 reg_val; |
| 291 | |
| 292 | reg_val = readl(&priv->regs->ctrl); |
| 293 | reg_val |= 0x11 << cs; |
| 294 | writel(reg_val, &priv->regs->ctrl); |
| 295 | } |
| 296 | |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 297 | static int ast2600_adjust_decoded_size(struct udevice *bus) |
| 298 | { |
| 299 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 300 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 301 | struct aspeed_spi_flash *flashes = &priv->flashes[0]; |
| 302 | int ret; |
| 303 | int i; |
| 304 | int cs; |
| 305 | u32 pre_sz; |
| 306 | u32 lack_sz; |
| 307 | |
| 308 | /* Close unused CS. */ |
| 309 | for (cs = priv->num_cs; cs < plat->max_cs; cs++) |
| 310 | flashes[cs].ahb_decoded_sz = 0; |
| 311 | |
| 312 | /* |
| 313 | * If commnad mode or normal mode is used, the start address of a |
| 314 | * decoded range should be multiple of its related flash size. |
| 315 | * Namely, the total decoded size from flash 0 to flash N should |
| 316 | * be multiple of the size of flash (N + 1). |
| 317 | */ |
| 318 | for (cs = priv->num_cs - 1; cs >= 0; cs--) { |
| 319 | pre_sz = 0; |
| 320 | for (i = 0; i < cs; i++) |
| 321 | pre_sz += flashes[i].ahb_decoded_sz; |
| 322 | |
| 323 | if (flashes[cs].ahb_decoded_sz != 0 && |
| 324 | (pre_sz % flashes[cs].ahb_decoded_sz) != 0) { |
| 325 | lack_sz = flashes[cs].ahb_decoded_sz - |
| 326 | (pre_sz % flashes[cs].ahb_decoded_sz); |
| 327 | flashes[0].ahb_decoded_sz += lack_sz; |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | ret = aspeed_spi_trim_decoded_size(bus); |
| 332 | if (ret != 0) |
| 333 | return ret; |
| 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | /* |
| 339 | * As the flash size grows up, we need to trim some decoded |
| 340 | * size if needed for the sake of conforming the maximum |
| 341 | * decoded size. We trim the decoded size from the largest |
| 342 | * CS in order to avoid affecting the default boot up sequence |
| 343 | * from CS0 where command mode or normal mode is used. |
| 344 | * Notice, if a CS decoded size is trimmed, command mode may |
| 345 | * not work perfectly on that CS. |
| 346 | */ |
| 347 | static int aspeed_spi_trim_decoded_size(struct udevice *bus) |
| 348 | { |
| 349 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 350 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 351 | struct aspeed_spi_flash *flashes = &priv->flashes[0]; |
| 352 | u32 total_sz; |
| 353 | int cs = plat->max_cs - 1; |
| 354 | u32 i; |
| 355 | |
| 356 | do { |
| 357 | total_sz = 0; |
| 358 | for (i = 0; i < plat->max_cs; i++) |
| 359 | total_sz += flashes[i].ahb_decoded_sz; |
| 360 | |
| 361 | if (flashes[cs].ahb_decoded_sz <= priv->info->min_decoded_sz) |
| 362 | cs--; |
| 363 | |
| 364 | if (cs < 0) |
| 365 | return -ENOMEM; |
| 366 | |
| 367 | if (total_sz > plat->ahb_sz) { |
| 368 | flashes[cs].ahb_decoded_sz -= |
| 369 | priv->info->min_decoded_sz; |
| 370 | total_sz -= priv->info->min_decoded_sz; |
| 371 | } |
| 372 | } while (total_sz > plat->ahb_sz); |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 377 | static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, |
| 378 | size_t len) |
| 379 | { |
| 380 | size_t offset = 0; |
| 381 | |
| 382 | if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && |
| 383 | IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { |
| 384 | readsl(ahb_base, buf, len >> 2); |
| 385 | offset = len & ~0x3; |
| 386 | len -= offset; |
| 387 | } |
| 388 | |
| 389 | readsb(ahb_base, (u8 *)buf + offset, len); |
| 390 | |
| 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, |
| 395 | size_t len) |
| 396 | { |
| 397 | size_t offset = 0; |
| 398 | |
| 399 | if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && |
| 400 | IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { |
| 401 | writesl(ahb_base, buf, len >> 2); |
| 402 | offset = len & ~0x3; |
| 403 | len -= offset; |
| 404 | } |
| 405 | |
| 406 | writesb(ahb_base, (u8 *)buf + offset, len); |
| 407 | |
| 408 | return 0; |
| 409 | } |
| 410 | |
| 411 | /* |
| 412 | * Currently, only support 1-1-1, 1-1-2 or 1-1-4 |
| 413 | * SPI NOR flash operation format. |
| 414 | */ |
| 415 | static bool aspeed_spi_supports_op(struct spi_slave *slave, |
| 416 | const struct spi_mem_op *op) |
| 417 | { |
| 418 | struct udevice *bus = slave->dev->parent; |
| 419 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 420 | |
| 421 | if (op->cmd.buswidth > 1) |
| 422 | return false; |
| 423 | |
| 424 | if (op->addr.nbytes != 0) { |
| 425 | if (op->addr.buswidth > 1) |
| 426 | return false; |
| 427 | if (op->addr.nbytes < 3 || op->addr.nbytes > 4) |
| 428 | return false; |
| 429 | } |
| 430 | |
| 431 | if (op->dummy.nbytes != 0) { |
| 432 | if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7) |
| 433 | return false; |
| 434 | } |
| 435 | |
| 436 | if (op->data.nbytes != 0 && |
| 437 | op->data.buswidth > priv->info->max_bus_width) |
| 438 | return false; |
| 439 | |
| 440 | if (!spi_mem_default_supports_op(slave, op)) |
| 441 | return false; |
| 442 | |
| 443 | return true; |
| 444 | } |
| 445 | |
| 446 | static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, |
| 447 | const struct spi_mem_op *op) |
| 448 | { |
| 449 | struct udevice *dev = slave->dev; |
| 450 | struct udevice *bus = dev->parent; |
| 451 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 452 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); |
| 453 | u32 cs = slave_plat->cs; |
| 454 | u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; |
| 455 | u32 ce_ctrl_val; |
| 456 | struct aspeed_spi_flash *flash = &priv->flashes[cs]; |
| 457 | u8 dummy_data[16] = {0}; |
| 458 | u8 addr[4] = {0}; |
| 459 | int i; |
| 460 | |
| 461 | dev_dbg(dev, "cmd:%x(%d),addr:%llx(%d),dummy:%d(%d),data_len:0x%x(%d)\n", |
| 462 | op->cmd.opcode, op->cmd.buswidth, op->addr.val, |
| 463 | op->addr.buswidth, op->dummy.nbytes, op->dummy.buswidth, |
| 464 | op->data.nbytes, op->data.buswidth); |
| 465 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 466 | if (priv->info == &ast2400_spi_info) |
| 467 | ce_ctrl_reg = (u32)&priv->regs->ctrl; |
| 468 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 469 | /* |
| 470 | * Set controller to 4-byte address mode |
| 471 | * if flash is in 4-byte address mode. |
| 472 | */ |
| 473 | if (op->cmd.opcode == SPINOR_OP_EN4B) |
| 474 | priv->info->set_4byte(bus, cs); |
| 475 | |
| 476 | /* Start user mode */ |
| 477 | ce_ctrl_val = flash->ce_ctrl_user; |
| 478 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 479 | ce_ctrl_val &= (~CTRL_STOP_ACTIVE); |
| 480 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 481 | |
| 482 | /* Send command */ |
| 483 | aspeed_spi_write_to_ahb(flash->ahb_base, &op->cmd.opcode, 1); |
| 484 | |
| 485 | /* Send address */ |
| 486 | for (i = op->addr.nbytes; i > 0; i--) { |
| 487 | addr[op->addr.nbytes - i] = |
| 488 | ((u32)op->addr.val >> ((i - 1) * 8)) & 0xff; |
| 489 | } |
| 490 | |
| 491 | /* Change io_mode */ |
| 492 | ce_ctrl_val &= ~priv->info->io_mode_mask; |
| 493 | ce_ctrl_val |= aspeed_spi_get_io_mode(op->addr.buswidth); |
| 494 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 495 | aspeed_spi_write_to_ahb(flash->ahb_base, addr, op->addr.nbytes); |
| 496 | |
| 497 | /* Send dummy cycles */ |
| 498 | aspeed_spi_write_to_ahb(flash->ahb_base, dummy_data, op->dummy.nbytes); |
| 499 | |
| 500 | /* Change io_mode */ |
| 501 | ce_ctrl_val &= ~priv->info->io_mode_mask; |
| 502 | ce_ctrl_val |= aspeed_spi_get_io_mode(op->data.buswidth); |
| 503 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 504 | |
| 505 | /* Send data */ |
| 506 | if (op->data.dir == SPI_MEM_DATA_OUT) { |
| 507 | aspeed_spi_write_to_ahb(flash->ahb_base, op->data.buf.out, |
| 508 | op->data.nbytes); |
| 509 | } else { |
| 510 | aspeed_spi_read_from_ahb(flash->ahb_base, op->data.buf.in, |
| 511 | op->data.nbytes); |
| 512 | } |
| 513 | |
| 514 | ce_ctrl_val |= CTRL_STOP_ACTIVE; |
| 515 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 516 | |
| 517 | /* Restore controller setting. */ |
| 518 | writel(flash->ce_ctrl_read, ce_ctrl_reg); |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
Chin-Ting Kuo | 992d02e | 2022-08-19 17:01:10 +0800 | [diff] [blame] | 523 | static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) |
| 524 | { |
| 525 | int ret = 0; |
| 526 | struct udevice *dev = desc->slave->dev; |
| 527 | struct udevice *bus = dev->parent; |
| 528 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 529 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 530 | const struct aspeed_spi_info *info = priv->info; |
| 531 | struct spi_mem_op op_tmpl = desc->info.op_tmpl; |
| 532 | u32 i; |
| 533 | u32 cs = slave_plat->cs; |
| 534 | u32 reg_val; |
| 535 | u32 ce_ctrl_reg; |
| 536 | |
| 537 | if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { |
| 538 | /* |
| 539 | * dirmap_write is not supported currently due to a HW |
| 540 | * limitation for command write mode: The written data |
| 541 | * length should be multiple of 4-byte. |
| 542 | */ |
| 543 | return -EOPNOTSUPP; |
| 544 | } |
| 545 | |
| 546 | ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; |
| 547 | if (info == &ast2400_spi_info) |
| 548 | ce_ctrl_reg = (u32)&priv->regs->ctrl; |
| 549 | |
| 550 | if (desc->info.length > 0x1000000) |
| 551 | priv->info->set_4byte(bus, cs); |
| 552 | |
| 553 | /* AST2400 SPI1 doesn't have decoded address segment register. */ |
| 554 | if (info != &ast2400_spi_info) { |
| 555 | priv->flashes[cs].ahb_decoded_sz = desc->info.length; |
| 556 | |
| 557 | for (i = 0; i < priv->num_cs; i++) { |
| 558 | dev_dbg(dev, "cs: %d, sz: 0x%x\n", i, |
| 559 | priv->flashes[cs].ahb_decoded_sz); |
| 560 | } |
| 561 | |
| 562 | ret = aspeed_spi_decoded_range_config(bus); |
| 563 | if (ret) |
| 564 | return ret; |
| 565 | } |
| 566 | |
| 567 | reg_val = aspeed_spi_get_io_mode(op_tmpl.data.buswidth) | |
| 568 | op_tmpl.cmd.opcode << 16 | |
| 569 | ((op_tmpl.dummy.nbytes) & 0x3) << 6 | |
| 570 | ((op_tmpl.dummy.nbytes) & 0x4) << 14 | |
| 571 | CTRL_IO_MODE_CMD_READ; |
| 572 | |
| 573 | writel(reg_val, ce_ctrl_reg); |
| 574 | |
| 575 | priv->flashes[cs].ce_ctrl_read = reg_val; |
| 576 | |
| 577 | dev_dbg(dev, "read bus width: %d ce_ctrl_val: 0x%08x\n", |
| 578 | op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read); |
| 579 | |
| 580 | return ret; |
| 581 | } |
| 582 | |
| 583 | static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, |
| 584 | u64 offs, size_t len, void *buf) |
| 585 | { |
| 586 | struct udevice *dev = desc->slave->dev; |
| 587 | struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); |
| 588 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 589 | u32 cs = slave_plat->cs; |
| 590 | int ret; |
| 591 | |
| 592 | dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n", |
| 593 | desc->info.op_tmpl.cmd.opcode, offs, len); |
| 594 | |
| 595 | if (priv->flashes[cs].ahb_decoded_sz < offs + len || |
| 596 | (offs % 4) != 0) { |
| 597 | ret = aspeed_spi_exec_op_user_mode(desc->slave, |
| 598 | &desc->info.op_tmpl); |
| 599 | if (ret != 0) |
| 600 | return 0; |
| 601 | } else { |
| 602 | memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len); |
| 603 | } |
| 604 | |
| 605 | return len; |
| 606 | } |
| 607 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 608 | static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) |
| 609 | { |
| 610 | struct udevice *bus = dev->parent; |
| 611 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 612 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 613 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 614 | u32 cs = slave_plat->cs; |
| 615 | |
| 616 | if (cs >= plat->max_cs) { |
| 617 | dev_err(dev, "invalid CS %u\n", cs); |
| 618 | return NULL; |
| 619 | } |
| 620 | |
| 621 | return &priv->flashes[cs]; |
| 622 | } |
| 623 | |
| 624 | static void aspeed_spi_decoded_base_calculate(struct udevice *bus) |
| 625 | { |
| 626 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 627 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 628 | u32 cs; |
| 629 | |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 630 | if (priv->fixed_decoded_range) |
| 631 | return; |
| 632 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 633 | priv->flashes[0].ahb_base = plat->ahb_base; |
| 634 | |
| 635 | for (cs = 1; cs < plat->max_cs; cs++) { |
| 636 | priv->flashes[cs].ahb_base = |
| 637 | priv->flashes[cs - 1].ahb_base + |
| 638 | priv->flashes[cs - 1].ahb_decoded_sz; |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | static void aspeed_spi_decoded_range_set(struct udevice *bus) |
| 643 | { |
| 644 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 645 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 646 | u32 decoded_reg_val; |
| 647 | u32 start_addr, end_addr; |
| 648 | u32 cs; |
| 649 | |
| 650 | for (cs = 0; cs < plat->max_cs; cs++) { |
| 651 | start_addr = (u32)priv->flashes[cs].ahb_base; |
| 652 | end_addr = (u32)priv->flashes[cs].ahb_base + |
| 653 | priv->flashes[cs].ahb_decoded_sz; |
| 654 | |
| 655 | decoded_reg_val = priv->info->segment_reg(start_addr, end_addr); |
| 656 | |
| 657 | writel(decoded_reg_val, &priv->regs->segment_addr[cs]); |
| 658 | |
| 659 | dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n", |
| 660 | cs, decoded_reg_val, start_addr, end_addr); |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | static int aspeed_spi_decoded_range_config(struct udevice *bus) |
| 665 | { |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 666 | int ret = 0; |
| 667 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 668 | |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 669 | if (priv->info->adjust_decoded_sz && |
| 670 | !priv->fixed_decoded_range) { |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 671 | ret = priv->info->adjust_decoded_sz(bus); |
| 672 | if (ret != 0) |
| 673 | return ret; |
| 674 | } |
| 675 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 676 | aspeed_spi_decoded_base_calculate(bus); |
| 677 | aspeed_spi_decoded_range_set(bus); |
| 678 | |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 679 | return ret; |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 680 | } |
| 681 | |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 682 | static int aspeed_spi_decoded_ranges_sanity(struct udevice *bus) |
| 683 | { |
| 684 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 685 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 686 | u32 cs; |
| 687 | u32 total_sz = 0; |
| 688 | |
| 689 | /* Check overall size. */ |
| 690 | for (cs = 0; cs < plat->max_cs; cs++) |
| 691 | total_sz += priv->flashes[cs].ahb_decoded_sz; |
| 692 | |
| 693 | if (total_sz > plat->ahb_sz) { |
| 694 | dev_err(bus, "invalid total size 0x%08x\n", total_sz); |
| 695 | return -EINVAL; |
| 696 | } |
| 697 | |
| 698 | /* Check each decoded range size for AST2500. */ |
| 699 | if (priv->info == &ast2500_fmc_info || |
| 700 | priv->info == &ast2500_spi_info) { |
| 701 | for (cs = 0; cs < plat->max_cs; cs++) { |
| 702 | if (priv->flashes[cs].ahb_decoded_sz < |
| 703 | priv->info->min_decoded_sz) { |
| 704 | dev_err(bus, "insufficient decoded range.\n"); |
| 705 | return -EINVAL; |
| 706 | } |
| 707 | } |
| 708 | } |
| 709 | |
| 710 | /* |
| 711 | * Check overlay. Here, we assume the deccded ranges and |
| 712 | * address base are monotonic increasing with CE#. |
| 713 | */ |
| 714 | for (cs = plat->max_cs - 1; cs > 0; cs--) { |
| 715 | if ((u32)priv->flashes[cs].ahb_base != 0 && |
| 716 | (u32)priv->flashes[cs].ahb_base < |
| 717 | (u32)priv->flashes[cs - 1].ahb_base + |
| 718 | priv->flashes[cs - 1].ahb_decoded_sz) { |
| 719 | dev_err(bus, "decoded range overlay 0x%08x 0x%08x\n", |
| 720 | (u32)priv->flashes[cs].ahb_base, |
| 721 | (u32)priv->flashes[cs - 1].ahb_base); |
| 722 | return -EINVAL; |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | return 0; |
| 727 | } |
| 728 | |
| 729 | static int aspeed_spi_read_fixed_decoded_ranges(struct udevice *bus) |
| 730 | { |
| 731 | int ret = 0; |
| 732 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 733 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 734 | const char *range_prop = "decoded-ranges"; |
| 735 | struct aspeed_spi_decoded_range ranges[ASPEED_SPI_MAX_CS]; |
| 736 | const struct property *prop; |
| 737 | u32 prop_sz; |
| 738 | u32 count; |
| 739 | u32 i; |
| 740 | |
| 741 | priv->fixed_decoded_range = false; |
| 742 | |
| 743 | prop = dev_read_prop(bus, range_prop, &prop_sz); |
| 744 | if (!prop) |
| 745 | return 0; |
| 746 | |
| 747 | count = prop_sz / sizeof(struct aspeed_spi_decoded_range); |
| 748 | if (count > plat->max_cs || count < priv->num_cs) { |
| 749 | dev_err(bus, "invalid '%s' property %d %d\n", |
| 750 | range_prop, count, priv->num_cs); |
| 751 | return -EINVAL; |
| 752 | } |
| 753 | |
| 754 | ret = dev_read_u32_array(bus, range_prop, (u32 *)ranges, count * 3); |
| 755 | if (ret) |
| 756 | return ret; |
| 757 | |
| 758 | for (i = 0; i < count; i++) { |
| 759 | priv->flashes[ranges[i].cs].ahb_base = |
| 760 | (void __iomem *)ranges[i].ahb_base; |
| 761 | priv->flashes[ranges[i].cs].ahb_decoded_sz = |
| 762 | ranges[i].sz; |
| 763 | } |
| 764 | |
| 765 | for (i = 0; i < plat->max_cs; i++) { |
| 766 | dev_dbg(bus, "ahb_base: 0x%p, size: 0x%08x\n", |
| 767 | priv->flashes[i].ahb_base, |
| 768 | priv->flashes[i].ahb_decoded_sz); |
| 769 | } |
| 770 | |
| 771 | ret = aspeed_spi_decoded_ranges_sanity(bus); |
| 772 | if (ret != 0) |
| 773 | return ret; |
| 774 | |
| 775 | priv->fixed_decoded_range = true; |
| 776 | |
| 777 | return 0; |
| 778 | } |
| 779 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 780 | /* |
| 781 | * Initialize SPI controller for each chip select. |
| 782 | * Here, only the minimum decode range is configured |
| 783 | * in order to get device (SPI NOR flash) information |
| 784 | * at the early stage. |
| 785 | */ |
| 786 | static int aspeed_spi_ctrl_init(struct udevice *bus) |
| 787 | { |
| 788 | int ret; |
| 789 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 790 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 791 | u32 cs; |
| 792 | u32 reg_val; |
| 793 | u32 decoded_sz; |
| 794 | |
| 795 | /* Enable write capability for all CS. */ |
| 796 | reg_val = readl(&priv->regs->conf); |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 797 | if (priv->info == &ast2400_spi_info) { |
| 798 | writel(reg_val | BIT(0), &priv->regs->conf); |
| 799 | } else { |
| 800 | writel(reg_val | (GENMASK(plat->max_cs - 1, 0) << 16), |
| 801 | &priv->regs->conf); |
| 802 | } |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 803 | |
| 804 | memset(priv->flashes, 0x0, |
| 805 | sizeof(struct aspeed_spi_flash) * ASPEED_SPI_MAX_CS); |
| 806 | |
| 807 | /* Initial user mode. */ |
| 808 | for (cs = 0; cs < priv->num_cs; cs++) { |
| 809 | priv->flashes[cs].ce_ctrl_user = |
| 810 | (CTRL_STOP_ACTIVE | CTRL_IO_MODE_USER); |
| 811 | } |
| 812 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 813 | /* |
| 814 | * SPI1 on AST2400 only supports CS0. |
| 815 | * It is unnecessary to configure segment address register. |
| 816 | */ |
| 817 | if (priv->info == &ast2400_spi_info) { |
| 818 | priv->flashes[cs].ahb_base = plat->ahb_base; |
| 819 | priv->flashes[cs].ahb_decoded_sz = 0x10000000; |
| 820 | return 0; |
| 821 | } |
| 822 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 823 | |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 824 | ret = aspeed_spi_read_fixed_decoded_ranges(bus); |
| 825 | if (ret != 0) |
| 826 | return ret; |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 827 | |
Chin-Ting Kuo | dd29cee | 2022-08-19 17:01:13 +0800 | [diff] [blame^] | 828 | if (!priv->fixed_decoded_range) { |
| 829 | /* Assign basic AHB decoded size for each CS. */ |
| 830 | for (cs = 0; cs < plat->max_cs; cs++) { |
| 831 | reg_val = readl(&priv->regs->segment_addr[cs]); |
| 832 | decoded_sz = priv->info->segment_end(bus, reg_val) - |
| 833 | priv->info->segment_start(bus, reg_val); |
| 834 | |
| 835 | if (decoded_sz < priv->info->min_decoded_sz) |
| 836 | decoded_sz = priv->info->min_decoded_sz; |
| 837 | |
| 838 | priv->flashes[cs].ahb_decoded_sz = decoded_sz; |
| 839 | } |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 840 | } |
| 841 | |
| 842 | ret = aspeed_spi_decoded_range_config(bus); |
| 843 | |
| 844 | return ret; |
| 845 | } |
| 846 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 847 | static const struct aspeed_spi_info ast2400_fmc_info = { |
| 848 | .io_mode_mask = 0x70000000, |
| 849 | .max_bus_width = 2, |
| 850 | .min_decoded_sz = 0x800000, |
| 851 | .set_4byte = ast2400_fmc_chip_set_4byte, |
| 852 | .segment_start = ast2400_spi_segment_start, |
| 853 | .segment_end = ast2400_spi_segment_end, |
| 854 | .segment_reg = ast2400_spi_segment_reg, |
| 855 | }; |
| 856 | |
| 857 | static const struct aspeed_spi_info ast2400_spi_info = { |
| 858 | .io_mode_mask = 0x70000000, |
| 859 | .max_bus_width = 2, |
| 860 | .min_decoded_sz = 0x800000, |
| 861 | .set_4byte = ast2400_spi_chip_set_4byte, |
| 862 | .segment_start = ast2400_spi_segment_start, |
| 863 | .segment_end = ast2400_spi_segment_end, |
| 864 | .segment_reg = ast2400_spi_segment_reg, |
| 865 | }; |
| 866 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 867 | static const struct aspeed_spi_info ast2500_fmc_info = { |
| 868 | .io_mode_mask = 0x70000000, |
| 869 | .max_bus_width = 2, |
| 870 | .min_decoded_sz = 0x800000, |
| 871 | .set_4byte = ast2500_spi_chip_set_4byte, |
| 872 | .segment_start = ast2500_spi_segment_start, |
| 873 | .segment_end = ast2500_spi_segment_end, |
| 874 | .segment_reg = ast2500_spi_segment_reg, |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 875 | .adjust_decoded_sz = ast2500_adjust_decoded_size, |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 876 | }; |
| 877 | |
| 878 | /* |
| 879 | * There are some different between FMC and SPI controllers. |
| 880 | * For example, DMA operation, but this isn't implemented currently. |
| 881 | */ |
| 882 | static const struct aspeed_spi_info ast2500_spi_info = { |
| 883 | .io_mode_mask = 0x70000000, |
| 884 | .max_bus_width = 2, |
| 885 | .min_decoded_sz = 0x800000, |
| 886 | .set_4byte = ast2500_spi_chip_set_4byte, |
| 887 | .segment_start = ast2500_spi_segment_start, |
| 888 | .segment_end = ast2500_spi_segment_end, |
| 889 | .segment_reg = ast2500_spi_segment_reg, |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 890 | .adjust_decoded_sz = ast2500_adjust_decoded_size, |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 891 | }; |
| 892 | |
| 893 | static const struct aspeed_spi_info ast2600_fmc_info = { |
| 894 | .io_mode_mask = 0xf0000000, |
| 895 | .max_bus_width = 4, |
| 896 | .min_decoded_sz = 0x200000, |
| 897 | .set_4byte = ast2600_spi_chip_set_4byte, |
| 898 | .segment_start = ast2600_spi_segment_start, |
| 899 | .segment_end = ast2600_spi_segment_end, |
| 900 | .segment_reg = ast2600_spi_segment_reg, |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 901 | .adjust_decoded_sz = ast2600_adjust_decoded_size, |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 902 | }; |
| 903 | |
| 904 | static const struct aspeed_spi_info ast2600_spi_info = { |
| 905 | .io_mode_mask = 0xf0000000, |
| 906 | .max_bus_width = 4, |
| 907 | .min_decoded_sz = 0x200000, |
| 908 | .set_4byte = ast2600_spi_chip_set_4byte, |
| 909 | .segment_start = ast2600_spi_segment_start, |
| 910 | .segment_end = ast2600_spi_segment_end, |
| 911 | .segment_reg = ast2600_spi_segment_reg, |
Chin-Ting Kuo | 15a5c80 | 2022-08-19 17:01:12 +0800 | [diff] [blame] | 912 | .adjust_decoded_sz = ast2600_adjust_decoded_size, |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 913 | }; |
| 914 | |
| 915 | static int aspeed_spi_claim_bus(struct udevice *dev) |
| 916 | { |
| 917 | struct udevice *bus = dev->parent; |
| 918 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 919 | |
| 920 | dev_dbg(bus, "%s: claim bus CS%u\n", bus->name, slave_plat->cs); |
| 921 | |
| 922 | return 0; |
| 923 | } |
| 924 | |
| 925 | static int aspeed_spi_release_bus(struct udevice *dev) |
| 926 | { |
| 927 | struct udevice *bus = dev->parent; |
| 928 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 929 | |
| 930 | dev_dbg(bus, "%s: release bus CS%u\n", bus->name, slave_plat->cs); |
| 931 | |
| 932 | if (!aspeed_spi_get_flash(dev)) |
| 933 | return -ENODEV; |
| 934 | |
| 935 | return 0; |
| 936 | } |
| 937 | |
| 938 | static int aspeed_spi_set_mode(struct udevice *bus, uint mode) |
| 939 | { |
| 940 | dev_dbg(bus, "%s: setting mode to %x\n", bus->name, mode); |
| 941 | |
| 942 | return 0; |
| 943 | } |
| 944 | |
| 945 | static int aspeed_spi_set_speed(struct udevice *bus, uint hz) |
| 946 | { |
| 947 | dev_dbg(bus, "%s: setting speed to %u\n", bus->name, hz); |
| 948 | /* |
| 949 | * ASPEED SPI controller supports multiple CS with different |
| 950 | * clock frequency. We cannot distinguish which CS here. |
| 951 | * Thus, the related implementation is postponed to claim_bus. |
| 952 | */ |
| 953 | |
| 954 | return 0; |
| 955 | } |
| 956 | |
| 957 | static int apseed_spi_of_to_plat(struct udevice *bus) |
| 958 | { |
| 959 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 960 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 961 | |
| 962 | priv->regs = (void __iomem *)devfdt_get_addr_index(bus, 0); |
| 963 | if ((u32)priv->regs == FDT_ADDR_T_NONE) { |
| 964 | dev_err(bus, "wrong ctrl base\n"); |
| 965 | return -ENODEV; |
| 966 | } |
| 967 | |
| 968 | plat->ahb_base = |
| 969 | (void __iomem *)devfdt_get_addr_size_index(bus, 1, &plat->ahb_sz); |
| 970 | if ((u32)plat->ahb_base == FDT_ADDR_T_NONE) { |
| 971 | dev_err(bus, "wrong AHB base\n"); |
| 972 | return -ENODEV; |
| 973 | } |
| 974 | |
| 975 | plat->max_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); |
| 976 | if (plat->max_cs > ASPEED_SPI_MAX_CS) |
| 977 | return -EINVAL; |
| 978 | |
| 979 | dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%lx\n", |
| 980 | (u32)priv->regs, plat->ahb_base, plat->ahb_sz); |
| 981 | dev_dbg(bus, "max_cs = %d\n", plat->max_cs); |
| 982 | |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | static int aspeed_spi_probe(struct udevice *bus) |
| 987 | { |
| 988 | int ret; |
| 989 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 990 | struct udevice *dev; |
| 991 | |
| 992 | priv->info = (struct aspeed_spi_info *)dev_get_driver_data(bus); |
| 993 | |
| 994 | priv->num_cs = 0; |
| 995 | for (device_find_first_child(bus, &dev); dev; |
| 996 | device_find_next_child(&dev)) { |
| 997 | priv->num_cs++; |
| 998 | } |
| 999 | |
| 1000 | if (priv->num_cs > ASPEED_SPI_MAX_CS) |
| 1001 | return -EINVAL; |
| 1002 | |
| 1003 | ret = aspeed_spi_ctrl_init(bus); |
| 1004 | |
| 1005 | return ret; |
| 1006 | } |
| 1007 | |
| 1008 | static const struct spi_controller_mem_ops aspeed_spi_mem_ops = { |
| 1009 | .supports_op = aspeed_spi_supports_op, |
| 1010 | .exec_op = aspeed_spi_exec_op_user_mode, |
Chin-Ting Kuo | 992d02e | 2022-08-19 17:01:10 +0800 | [diff] [blame] | 1011 | .dirmap_create = aspeed_spi_dirmap_create, |
| 1012 | .dirmap_read = aspeed_spi_dirmap_read, |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 1013 | }; |
| 1014 | |
| 1015 | static const struct dm_spi_ops aspeed_spi_ops = { |
| 1016 | .claim_bus = aspeed_spi_claim_bus, |
| 1017 | .release_bus = aspeed_spi_release_bus, |
| 1018 | .set_speed = aspeed_spi_set_speed, |
| 1019 | .set_mode = aspeed_spi_set_mode, |
| 1020 | .mem_ops = &aspeed_spi_mem_ops, |
| 1021 | }; |
| 1022 | |
| 1023 | static const struct udevice_id aspeed_spi_ids[] = { |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 1024 | { .compatible = "aspeed,ast2400-fmc", .data = (ulong)&ast2400_fmc_info, }, |
| 1025 | { .compatible = "aspeed,ast2400-spi", .data = (ulong)&ast2400_spi_info, }, |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 1026 | { .compatible = "aspeed,ast2500-fmc", .data = (ulong)&ast2500_fmc_info, }, |
| 1027 | { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, }, |
| 1028 | { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, }, |
| 1029 | { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, }, |
| 1030 | { } |
| 1031 | }; |
| 1032 | |
| 1033 | U_BOOT_DRIVER(aspeed_spi) = { |
| 1034 | .name = "aspeed_spi_smc", |
| 1035 | .id = UCLASS_SPI, |
| 1036 | .of_match = aspeed_spi_ids, |
| 1037 | .ops = &aspeed_spi_ops, |
| 1038 | .of_to_plat = apseed_spi_of_to_plat, |
| 1039 | .plat_auto = sizeof(struct aspeed_spi_plat), |
| 1040 | .priv_auto = sizeof(struct aspeed_spi_priv), |
| 1041 | .probe = aspeed_spi_probe, |
| 1042 | }; |