blob: 5b6ea0e7599a28107413f045ade27475287f7dfb [file] [log] [blame]
Yen Lin96a78ac2012-03-06 19:00:23 +00001/*
2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <fdtdec.h>
27#include <i2c.h>
28#include <asm/io.h>
29#include <asm/arch/clk_rst.h>
30#include <asm/arch/clock.h>
31#include <asm/arch/funcmux.h>
32#include <asm/arch/gpio.h>
33#include <asm/arch/pinmux.h>
34#include <asm/arch/tegra_i2c.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38static unsigned int i2c_bus_num;
39
40/* Information about i2c controller */
41struct i2c_bus {
42 int id;
43 enum periph_id periph_id;
44 int speed;
45 int pinmux_config;
46 struct i2c_control *control;
47 struct i2c_ctlr *regs;
48 int is_dvc; /* DVC type, rather than I2C */
49 int inited; /* bus is inited */
50};
51
52static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
53
54static void set_packet_mode(struct i2c_bus *i2c_bus)
55{
56 u32 config;
57
58 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
59
60 if (i2c_bus->is_dvc) {
61 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
62
63 writel(config, &dvc->cnfg);
64 } else {
65 writel(config, &i2c_bus->regs->cnfg);
66 /*
67 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
68 * issues, i.e., some slaves may be wrongly detected.
69 */
70 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
71 }
72}
73
74static void i2c_reset_controller(struct i2c_bus *i2c_bus)
75{
76 /* Reset I2C controller. */
77 reset_periph(i2c_bus->periph_id, 1);
78
79 /* re-program config register to packet mode */
80 set_packet_mode(i2c_bus);
81}
82
83static void i2c_init_controller(struct i2c_bus *i2c_bus)
84{
85 /*
86 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
87 * here, in section 23.3.1, but in fact we seem to need a factor of
88 * 16 to get the right frequency.
89 */
90 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
91 i2c_bus->speed * 2 * 8);
92
93 /* Reset I2C controller. */
94 i2c_reset_controller(i2c_bus);
95
96 /* Configure I2C controller. */
97 if (i2c_bus->is_dvc) { /* only for DVC I2C */
98 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
99
100 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
101 }
102
103 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
104}
105
106static void send_packet_headers(
107 struct i2c_bus *i2c_bus,
108 struct i2c_trans_info *trans,
109 u32 packet_id)
110{
111 u32 data;
112
113 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
114 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
115 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
116 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
117 writel(data, &i2c_bus->control->tx_fifo);
118 debug("pkt header 1 sent (0x%x)\n", data);
119
120 /* prepare header2 */
121 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
122 writel(data, &i2c_bus->control->tx_fifo);
123 debug("pkt header 2 sent (0x%x)\n", data);
124
125 /* prepare IO specific header: configure the slave address */
126 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
127
128 /* Enable Read if it is not a write transaction */
129 if (!(trans->flags & I2C_IS_WRITE))
130 data |= PKT_HDR3_READ_MODE_MASK;
131
132 /* Write I2C specific header */
133 writel(data, &i2c_bus->control->tx_fifo);
134 debug("pkt header 3 sent (0x%x)\n", data);
135}
136
137static int wait_for_tx_fifo_empty(struct i2c_control *control)
138{
139 u32 count;
140 int timeout_us = I2C_TIMEOUT_USEC;
141
142 while (timeout_us >= 0) {
143 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
144 >> TX_FIFO_EMPTY_CNT_SHIFT;
145 if (count == I2C_FIFO_DEPTH)
146 return 1;
147 udelay(10);
148 timeout_us -= 10;
149 }
150
151 return 0;
152}
153
154static int wait_for_rx_fifo_notempty(struct i2c_control *control)
155{
156 u32 count;
157 int timeout_us = I2C_TIMEOUT_USEC;
158
159 while (timeout_us >= 0) {
160 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
161 >> TX_FIFO_FULL_CNT_SHIFT;
162 if (count)
163 return 1;
164 udelay(10);
165 timeout_us -= 10;
166 }
167
168 return 0;
169}
170
171static int wait_for_transfer_complete(struct i2c_control *control)
172{
173 int int_status;
174 int timeout_us = I2C_TIMEOUT_USEC;
175
176 while (timeout_us >= 0) {
177 int_status = readl(&control->int_status);
178 if (int_status & I2C_INT_NO_ACK_MASK)
179 return -int_status;
180 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
181 return -int_status;
182 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
183 return 0;
184
185 udelay(10);
186 timeout_us -= 10;
187 }
188
189 return -1;
190}
191
192static int send_recv_packets(struct i2c_bus *i2c_bus,
193 struct i2c_trans_info *trans)
194{
195 struct i2c_control *control = i2c_bus->control;
196 u32 int_status;
197 u32 words;
198 u8 *dptr;
199 u32 local;
200 uchar last_bytes;
201 int error = 0;
202 int is_write = trans->flags & I2C_IS_WRITE;
203
204 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
205 int_status = readl(&control->int_status);
206 writel(int_status, &control->int_status);
207
208 send_packet_headers(i2c_bus, trans, 1);
209
210 words = DIV_ROUND_UP(trans->num_bytes, 4);
211 last_bytes = trans->num_bytes & 3;
212 dptr = trans->buf;
213
214 while (words) {
215 u32 *wptr = (u32 *)dptr;
216
217 if (is_write) {
218 /* deal with word alignment */
219 if ((unsigned)dptr & 3) {
220 memcpy(&local, dptr, sizeof(u32));
221 writel(local, &control->tx_fifo);
222 debug("pkt data sent (0x%x)\n", local);
223 } else {
224 writel(*wptr, &control->tx_fifo);
225 debug("pkt data sent (0x%x)\n", *wptr);
226 }
227 if (!wait_for_tx_fifo_empty(control)) {
228 error = -1;
229 goto exit;
230 }
231 } else {
232 if (!wait_for_rx_fifo_notempty(control)) {
233 error = -1;
234 goto exit;
235 }
236 /*
237 * for the last word, we read into our local buffer,
238 * in case that caller did not provide enough buffer.
239 */
240 local = readl(&control->rx_fifo);
241 if ((words == 1) && last_bytes)
242 memcpy(dptr, (char *)&local, last_bytes);
243 else if ((unsigned)dptr & 3)
244 memcpy(dptr, &local, sizeof(u32));
245 else
246 *wptr = local;
247 debug("pkt data received (0x%x)\n", local);
248 }
249 words--;
250 dptr += sizeof(u32);
251 }
252
253 if (wait_for_transfer_complete(control)) {
254 error = -1;
255 goto exit;
256 }
257 return 0;
258exit:
259 /* error, reset the controller. */
260 i2c_reset_controller(i2c_bus);
261
262 return error;
263}
264
265static int tegra2_i2c_write_data(u32 addr, u8 *data, u32 len)
266{
267 int error;
268 struct i2c_trans_info trans_info;
269
270 trans_info.address = addr;
271 trans_info.buf = data;
272 trans_info.flags = I2C_IS_WRITE;
273 trans_info.num_bytes = len;
274 trans_info.is_10bit_address = 0;
275
276 error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
277 if (error)
278 debug("tegra2_i2c_write_data: Error (%d) !!!\n", error);
279
280 return error;
281}
282
283static int tegra2_i2c_read_data(u32 addr, u8 *data, u32 len)
284{
285 int error;
286 struct i2c_trans_info trans_info;
287
288 trans_info.address = addr | 1;
289 trans_info.buf = data;
290 trans_info.flags = 0;
291 trans_info.num_bytes = len;
292 trans_info.is_10bit_address = 0;
293
294 error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
295 if (error)
296 debug("tegra2_i2c_read_data: Error (%d) !!!\n", error);
297
298 return error;
299}
300
301#ifndef CONFIG_OF_CONTROL
302#error "Please enable device tree support to use this driver"
303#endif
304
305unsigned int i2c_get_bus_speed(void)
306{
307 return i2c_controllers[i2c_bus_num].speed;
308}
309
310int i2c_set_bus_speed(unsigned int speed)
311{
312 struct i2c_bus *i2c_bus;
313
314 i2c_bus = &i2c_controllers[i2c_bus_num];
315 i2c_bus->speed = speed;
316 i2c_init_controller(i2c_bus);
317
318 return 0;
319}
320
321static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
322{
323 i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
324
325 /*
326 * We don't have a binding for pinmux yet. Leave it out for now. So
327 * far no one needs anything other than the default.
328 */
329 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
330 i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
331 i2c_bus->periph_id = clock_decode_periph_id(blob, node);
332
333 /*
334 * We can't specify the pinmux config in the fdt, so I2C2 will not
335 * work on Seaboard. It normally has no devices on it anyway.
336 * You could add in this little hack if you need to use it.
337 * The correct solution is a pinmux binding in the fdt.
338 *
339 * if (i2c_bus->periph_id == PERIPH_ID_I2C2)
340 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
341 */
342 if (i2c_bus->periph_id == -1)
343 return -FDT_ERR_NOTFOUND;
344
345 return 0;
346}
347
348/*
349 * Process a list of nodes, adding them to our list of I2C ports.
350 *
351 * @param blob fdt blob
352 * @param node_list list of nodes to process (any <=0 are ignored)
353 * @param count number of nodes to process
354 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
355 * @return 0 if ok, -1 on error
356 */
357static int process_nodes(const void *blob, int node_list[], int count,
358 int is_dvc)
359{
360 struct i2c_bus *i2c_bus;
361 int i;
362
363 /* build the i2c_controllers[] for each controller */
364 for (i = 0; i < count; i++) {
365 int node = node_list[i];
366
367 if (node <= 0)
368 continue;
369
370 i2c_bus = &i2c_controllers[i];
371 i2c_bus->id = i;
372
373 if (i2c_get_config(blob, node, i2c_bus)) {
374 printf("i2c_init_board: failed to decode bus %d\n", i);
375 return -1;
376 }
377
378 i2c_bus->is_dvc = is_dvc;
379 if (is_dvc) {
380 i2c_bus->control =
381 &((struct dvc_ctlr *)i2c_bus->regs)->control;
382 } else {
383 i2c_bus->control = &i2c_bus->regs->control;
384 }
385 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
386 is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
387 i2c_bus->periph_id, i2c_bus->speed);
388 i2c_init_controller(i2c_bus);
389 debug("ok\n");
390 i2c_bus->inited = 1;
391
392 /* Mark position as used */
393 node_list[i] = -1;
394 }
395
396 return 0;
397}
398
399/* Sadly there is no error return from this function */
400void i2c_init_board(void)
401{
402 int node_list[TEGRA_I2C_NUM_CONTROLLERS];
403 const void *blob = gd->fdt_blob;
404 int count;
405
406 /* First get the normal i2c ports */
407 count = fdtdec_find_aliases_for_id(blob, "i2c",
408 COMPAT_NVIDIA_TEGRA20_I2C, node_list,
409 TEGRA_I2C_NUM_CONTROLLERS);
410 if (process_nodes(blob, node_list, count, 0))
411 return;
412
413 /* Now look for dvc ports */
414 count = fdtdec_add_aliases_for_id(blob, "i2c",
415 COMPAT_NVIDIA_TEGRA20_DVC, node_list,
416 TEGRA_I2C_NUM_CONTROLLERS);
417 if (process_nodes(blob, node_list, count, 1))
418 return;
419}
420
421void i2c_init(int speed, int slaveaddr)
422{
423 /* This will override the speed selected in the fdt for that port */
424 debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
425 i2c_set_bus_speed(speed);
426}
427
428/* i2c write version without the register address */
429int i2c_write_data(uchar chip, uchar *buffer, int len)
430{
431 int rc;
432
433 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
434 debug("write_data: ");
435 /* use rc for counter */
436 for (rc = 0; rc < len; ++rc)
437 debug(" 0x%02x", buffer[rc]);
438 debug("\n");
439
440 /* Shift 7-bit address over for lower-level i2c functions */
441 rc = tegra2_i2c_write_data(chip << 1, buffer, len);
442 if (rc)
443 debug("i2c_write_data(): rc=%d\n", rc);
444
445 return rc;
446}
447
448/* i2c read version without the register address */
449int i2c_read_data(uchar chip, uchar *buffer, int len)
450{
451 int rc;
452
453 debug("inside i2c_read_data():\n");
454 /* Shift 7-bit address over for lower-level i2c functions */
455 rc = tegra2_i2c_read_data(chip << 1, buffer, len);
456 if (rc) {
457 debug("i2c_read_data(): rc=%d\n", rc);
458 return rc;
459 }
460
461 debug("i2c_read_data: ");
462 /* reuse rc for counter*/
463 for (rc = 0; rc < len; ++rc)
464 debug(" 0x%02x", buffer[rc]);
465 debug("\n");
466
467 return 0;
468}
469
470/* Probe to see if a chip is present. */
471int i2c_probe(uchar chip)
472{
473 int rc;
474 uchar reg;
475
476 debug("i2c_probe: addr=0x%x\n", chip);
477 reg = 0;
478 rc = i2c_write_data(chip, &reg, 1);
479 if (rc) {
480 debug("Error probing 0x%x.\n", chip);
481 return 1;
482 }
483 return 0;
484}
485
486static int i2c_addr_ok(const uint addr, const int alen)
487{
488 /* We support 7 or 10 bit addresses, so one or two bytes each */
489 return alen == 1 || alen == 2;
490}
491
492/* Read bytes */
493int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
494{
495 uint offset;
496 int i;
497
498 debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
499 chip, addr, len);
500 if (!i2c_addr_ok(addr, alen)) {
501 debug("i2c_read: Bad address %x.%d.\n", addr, alen);
502 return 1;
503 }
504 for (offset = 0; offset < len; offset++) {
505 if (alen) {
506 uchar data[alen];
507 for (i = 0; i < alen; i++) {
508 data[alen - i - 1] =
509 (addr + offset) >> (8 * i);
510 }
511 if (i2c_write_data(chip, data, alen)) {
512 debug("i2c_read: error sending (0x%x)\n",
513 addr);
514 return 1;
515 }
516 }
517 if (i2c_read_data(chip, buffer + offset, 1)) {
518 debug("i2c_read: error reading (0x%x)\n", addr);
519 return 1;
520 }
521 }
522
523 return 0;
524}
525
526/* Write bytes */
527int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
528{
529 uint offset;
530 int i;
531
532 debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
533 chip, addr, len);
534 if (!i2c_addr_ok(addr, alen)) {
535 debug("i2c_write: Bad address %x.%d.\n", addr, alen);
536 return 1;
537 }
538 for (offset = 0; offset < len; offset++) {
539 uchar data[alen + 1];
540 for (i = 0; i < alen; i++)
541 data[alen - i - 1] = (addr + offset) >> (8 * i);
542 data[alen] = buffer[offset];
543 if (i2c_write_data(chip, data, alen + 1)) {
544 debug("i2c_write: error sending (0x%x)\n", addr);
545 return 1;
546 }
547 }
548
549 return 0;
550}
551
552#if defined(CONFIG_I2C_MULTI_BUS)
553/*
554 * Functions for multiple I2C bus handling
555 */
556unsigned int i2c_get_bus_num(void)
557{
558 return i2c_bus_num;
559}
560
561int i2c_set_bus_num(unsigned int bus)
562{
563 if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited)
564 return -1;
565 i2c_bus_num = bus;
566
567 return 0;
568}
569#endif
Simon Glasse31c1e52012-04-02 13:19:01 +0000570
571int tegra_i2c_get_dvc_bus_num(void)
572{
573 int i;
574
575 for (i = 0; i < CONFIG_SYS_MAX_I2C_BUS; i++) {
576 struct i2c_bus *bus = &i2c_controllers[i];
577
578 if (bus->inited && bus->is_dvc)
579 return i;
580 }
581
582 return -1;
583}