Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 2 | /* |
3 | * Copyright (C) 2016 Google, Inc | ||||
4 | * Written by Simon Glass <sjg@chromium.org> | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 5 | */ |
6 | |||||
7 | #include <config.h> | ||||
8 | |||||
Simon Glass | c5edefb | 2019-05-02 10:52:20 -0600 | [diff] [blame] | 9 | #ifdef CONFIG_CHROMEOS |
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 10 | / { |
11 | binman { | ||||
Simon Glass | c5edefb | 2019-05-02 10:52:20 -0600 | [diff] [blame] | 12 | multiple-images; |
13 | rom: rom { | ||||
14 | }; | ||||
15 | }; | ||||
16 | }; | ||||
17 | #else | ||||
18 | / { | ||||
19 | rom: binman { | ||||
20 | }; | ||||
21 | }; | ||||
22 | #endif | ||||
23 | |||||
24 | #ifdef CONFIG_ROM_SIZE | ||||
25 | &rom { | ||||
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 26 | filename = "u-boot.rom"; |
27 | end-at-4gb; | ||||
28 | sort-by-offset; | ||||
29 | pad-byte = <0xff>; | ||||
30 | size = <CONFIG_ROM_SIZE>; | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 31 | #ifdef CONFIG_HAVE_INTEL_ME |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 32 | intel-descriptor { |
33 | filename = CONFIG_FLASH_DESCRIPTOR_FILE; | ||||
34 | }; | ||||
35 | intel-me { | ||||
36 | filename = CONFIG_INTEL_ME_FILE; | ||||
37 | }; | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 38 | #endif |
Simon Glass | 93c7607 | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 39 | #ifdef CONFIG_TPL |
Simon Glass | 86a8fb3 | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 40 | #ifdef CONFIG_HAVE_MICROCODE |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 41 | u-boot-tpl-with-ucode-ptr { |
42 | offset = <CONFIG_TPL_TEXT_BASE>; | ||||
43 | }; | ||||
44 | u-boot-tpl-dtb { | ||||
45 | }; | ||||
Simon Glass | 86a8fb3 | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 46 | #endif |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 47 | u-boot-spl { |
48 | offset = <CONFIG_SPL_TEXT_BASE>; | ||||
49 | }; | ||||
50 | u-boot-spl-dtb { | ||||
51 | }; | ||||
52 | u-boot { | ||||
53 | offset = <CONFIG_SYS_TEXT_BASE>; | ||||
54 | }; | ||||
Simon Glass | 93c7607 | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 55 | #elif defined(CONFIG_SPL) |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 56 | u-boot-spl-with-ucode-ptr { |
57 | offset = <CONFIG_SPL_TEXT_BASE>; | ||||
58 | }; | ||||
59 | u-boot-dtb-with-ucode2 { | ||||
60 | type = "u-boot-dtb-with-ucode"; | ||||
61 | }; | ||||
62 | u-boot { | ||||
Simon Glass | 93c7607 | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 63 | /* |
64 | * TODO(sjg@chromium.org): | ||||
65 | * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But | ||||
66 | * for boards with textbase in SDRAM we cannot do this. Just use | ||||
67 | * an assumed-valid value (1MB before the end of flash) here so | ||||
68 | * that we can actually build an image for coreboot, etc. | ||||
69 | * We need a better solution, perhaps a separate Kconfig. | ||||
70 | */ | ||||
71 | #if CONFIG_SYS_TEXT_BASE == 0x1110000 | ||||
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 72 | offset = <0xfff00000>; |
Simon Glass | 93c7607 | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 73 | #else |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 74 | offset = <CONFIG_SYS_TEXT_BASE>; |
Simon Glass | 93c7607 | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 75 | #endif |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 76 | }; |
Simon Glass | 164f041 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 77 | #else |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 78 | u-boot-with-ucode-ptr { |
79 | offset = <CONFIG_SYS_TEXT_BASE>; | ||||
80 | }; | ||||
Simon Glass | 164f041 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 81 | #endif |
Simon Glass | 86a8fb3 | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 82 | #ifdef CONFIG_HAVE_MICROCODE |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 83 | u-boot-dtb-with-ucode { |
84 | }; | ||||
85 | u-boot-ucode { | ||||
86 | align = <16>; | ||||
87 | }; | ||||
Simon Glass | 86a8fb3 | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 88 | #else |
89 | u-boot-dtb { | ||||
90 | }; | ||||
91 | #endif | ||||
Simon Glass | 2e2a003 | 2019-12-06 21:42:24 -0700 | [diff] [blame] | 92 | #ifdef CONFIG_HAVE_X86_FIT |
93 | intel-fit { | ||||
94 | }; | ||||
95 | intel-fit-ptr { | ||||
96 | }; | ||||
97 | #endif | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 98 | #ifdef CONFIG_HAVE_MRC |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 99 | intel-mrc { |
100 | offset = <CONFIG_X86_MRC_ADDR>; | ||||
101 | }; | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 102 | #endif |
Simon Glass | dda8e3e | 2019-12-06 21:42:28 -0700 | [diff] [blame^] | 103 | #ifdef CONFIG_FSP_VERSION1 |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 104 | intel-fsp { |
105 | filename = CONFIG_FSP_FILE; | ||||
106 | offset = <CONFIG_FSP_ADDR>; | ||||
107 | }; | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 108 | #endif |
Simon Glass | dda8e3e | 2019-12-06 21:42:28 -0700 | [diff] [blame^] | 109 | #ifdef CONFIG_FSP_VERSION2 |
110 | intel-descriptor { | ||||
111 | filename = CONFIG_FLASH_DESCRIPTOR_FILE; | ||||
112 | }; | ||||
113 | intel-ifwi { | ||||
114 | filename = CONFIG_IFWI_INPUT_FILE; | ||||
115 | convert-fit; | ||||
116 | |||||
117 | section { | ||||
118 | size = <0x8000>; | ||||
119 | ifwi-replace; | ||||
120 | ifwi-subpart = "IBBP"; | ||||
121 | ifwi-entry = "IBBL"; | ||||
122 | u-boot-tpl { | ||||
123 | }; | ||||
124 | x86-start16-tpl { | ||||
125 | offset = <0x7800>; | ||||
126 | }; | ||||
127 | x86-reset16-tpl { | ||||
128 | offset = <0x7ff0>; | ||||
129 | }; | ||||
130 | }; | ||||
131 | }; | ||||
132 | intel-fsp-m { | ||||
133 | filename = CONFIG_FSP_FILE_M; | ||||
134 | }; | ||||
135 | intel-fsp-s { | ||||
136 | filename = CONFIG_FSP_FILE_S; | ||||
137 | }; | ||||
138 | #endif | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 139 | #ifdef CONFIG_HAVE_CMC |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 140 | intel-cmc { |
141 | filename = CONFIG_CMC_FILE; | ||||
142 | offset = <CONFIG_CMC_ADDR>; | ||||
143 | }; | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 144 | #endif |
145 | #ifdef CONFIG_HAVE_VGA_BIOS | ||||
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 146 | intel-vga { |
147 | filename = CONFIG_VGA_BIOS_FILE; | ||||
148 | offset = <CONFIG_VGA_BIOS_ADDR>; | ||||
149 | }; | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 150 | #endif |
Bin Meng | 6c22379 | 2017-08-15 22:41:55 -0700 | [diff] [blame] | 151 | #ifdef CONFIG_HAVE_VBT |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 152 | intel-vbt { |
153 | filename = CONFIG_VBT_FILE; | ||||
154 | offset = <CONFIG_VBT_ADDR>; | ||||
155 | }; | ||||
Bin Meng | 6c22379 | 2017-08-15 22:41:55 -0700 | [diff] [blame] | 156 | #endif |
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 157 | #ifdef CONFIG_HAVE_REFCODE |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 158 | intel-refcode { |
159 | offset = <CONFIG_X86_REFCODE_ADDR>; | ||||
160 | }; | ||||
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 161 | #endif |
Simon Glass | 93c7607 | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 162 | #ifdef CONFIG_TPL |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 163 | x86-start16-tpl { |
164 | offset = <CONFIG_SYS_X86_START16>; | ||||
165 | }; | ||||
Simon Glass | 5e23918 | 2019-08-24 07:22:49 -0600 | [diff] [blame] | 166 | x86-reset16-tpl { |
167 | offset = <CONFIG_RESET_VEC_LOC>; | ||||
168 | }; | ||||
Simon Glass | 93c7607 | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 169 | #elif defined(CONFIG_SPL) |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 170 | x86-start16-spl { |
171 | offset = <CONFIG_SYS_X86_START16>; | ||||
172 | }; | ||||
Simon Glass | 5e23918 | 2019-08-24 07:22:49 -0600 | [diff] [blame] | 173 | x86-reset16-spl { |
174 | offset = <CONFIG_RESET_VEC_LOC>; | ||||
175 | }; | ||||
Simon Glass | 164f041 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 176 | #else |
Simon Glass | e766d9f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 177 | x86-start16 { |
178 | offset = <CONFIG_SYS_X86_START16>; | ||||
179 | }; | ||||
Simon Glass | 5e23918 | 2019-08-24 07:22:49 -0600 | [diff] [blame] | 180 | x86-reset16 { |
181 | offset = <CONFIG_RESET_VEC_LOC>; | ||||
182 | }; | ||||
Simon Glass | 164f041 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 183 | #endif |
Simon Glass | b215fbd | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 184 | }; |
185 | #endif |