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Masahiro Yamada238bd0b2015-01-13 12:44:37 +09001/*
2 * Copyright (C) 2014 Panasonic Corporation
Masahiro Yamada6462cde2015-03-11 15:54:46 +09003 * Copyright (C) 2015 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada238bd0b2015-01-13 12:44:37 +09005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <linux/types.h>
11#include <asm/io.h>
12#include <asm/errno.h>
13#include <dm/device.h>
14#include <dm/root.h>
15#include <i2c.h>
16#include <fdtdec.h>
Joe Hershberger0eb25b62015-03-22 17:08:59 -050017#include <mapmem.h>
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090018
19DECLARE_GLOBAL_DATA_PTR;
20
21struct uniphier_fi2c_regs {
22 u32 cr; /* control register */
23#define I2C_CR_MST (1 << 3) /* master mode */
24#define I2C_CR_STA (1 << 2) /* start condition */
25#define I2C_CR_STO (1 << 1) /* stop condition */
26#define I2C_CR_NACK (1 << 0) /* not ACK */
27 u32 dttx; /* send FIFO (write-only) */
28#define dtrx dttx /* receive FIFO (read-only) */
29#define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
30#define I2C_DTTX_RD (1 << 0) /* read */
31 u32 __reserved; /* no register at offset 0x08 */
32 u32 slad; /* slave address */
33 u32 cyc; /* clock cycle control */
34 u32 lctl; /* clock low period control */
35 u32 ssut; /* restart/stop setup time control */
36 u32 dsut; /* data setup time control */
37 u32 intr; /* interrupt status */
38 u32 ie; /* interrupt enable */
39 u32 ic; /* interrupt clear */
40#define I2C_INT_TE (1 << 9) /* TX FIFO empty */
41#define I2C_INT_RB (1 << 4) /* received specified bytes */
42#define I2C_INT_NA (1 << 2) /* no answer */
43#define I2C_INT_AL (1 << 1) /* arbitration lost */
44 u32 sr; /* status register */
45#define I2C_SR_DB (1 << 12) /* device busy */
46#define I2C_SR_BB (1 << 8) /* bus busy */
47#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
48#define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
49#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
50#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
51 u32 __reserved2; /* no register at offset 0x30 */
52 u32 rst; /* reset control */
53#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
54#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
55#define I2C_RST_RST (1 << 0) /* forcible bus reset */
56 u32 bm; /* bus monitor */
57 u32 noise; /* noise filter control */
58 u32 tbc; /* Tx byte count setting */
59 u32 rbc; /* Rx byte count setting */
60 u32 tbcm; /* Tx byte count monitor */
61 u32 rbcm; /* Rx byte count monitor */
62 u32 brst; /* bus reset */
63#define I2C_BRST_FOEN (1 << 1) /* normal operation */
64#define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
65};
66
67#define FIOCLK 50000000
68
69struct uniphier_fi2c_dev {
70 struct uniphier_fi2c_regs __iomem *regs; /* register base */
71 unsigned long fioclk; /* internal operation clock */
72 unsigned long timeout; /* time out (us) */
73};
74
75static int poll_status(u32 __iomem *reg, u32 flag)
76{
77 int wait = 1000000; /* 1 sec is long enough */
78
79 while (readl(reg) & flag) {
80 if (wait-- < 0)
81 return -EREMOTEIO;
82 udelay(1);
83 }
84
85 return 0;
86}
87
88static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
89{
90 int ret;
91
92 /* bus forcible reset */
93 writel(I2C_RST_RST, &regs->rst);
94 ret = poll_status(&regs->rst, I2C_RST_RST);
95 if (ret < 0)
96 debug("error: fail to reset I2C controller\n");
97
98 return ret;
99}
100
101static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
102{
103 int ret;
104
105 ret = poll_status(&regs->sr, I2C_SR_DB);
106 if (ret < 0) {
107 debug("error: device busy too long. reset...\n");
108 ret = reset_bus(regs);
109 }
110
111 return ret;
112}
113
114static int uniphier_fi2c_probe(struct udevice *dev)
115{
116 fdt_addr_t addr;
117 fdt_size_t size;
118 struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
119 int ret;
120
121 addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
122 &size);
123
124 priv->regs = map_sysmem(addr, size);
125
126 if (!priv->regs)
127 return -ENOMEM;
128
129 priv->fioclk = FIOCLK;
130
131 /* bus forcible reset */
132 ret = reset_bus(priv->regs);
133 if (ret < 0)
134 return ret;
135
136 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
137
138 return 0;
139}
140
141static int uniphier_fi2c_remove(struct udevice *dev)
142{
143 struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
144
145 unmap_sysmem(priv->regs);
146
147 return 0;
148}
149
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900150static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
151 bool *stop)
152{
153 u32 irq;
154 unsigned long wait = dev->timeout;
155 int ret = -EREMOTEIO;
156
157 do {
158 udelay(1);
159 irq = readl(&dev->regs->intr);
160 } while (!(irq & flags) && wait--);
161
162 if (wait < 0) {
163 debug("error: time out\n");
164 return ret;
165 }
166
167 if (irq & I2C_INT_AL) {
168 debug("error: arbitration lost\n");
169 *stop = false;
170 return ret;
171 }
172
173 if (irq & I2C_INT_NA) {
174 debug("error: no answer\n");
175 return ret;
176 }
177
178 return 0;
179}
180
181static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
182{
183 int ret;
184
185 debug("stop condition\n");
186 writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
187
188 ret = poll_status(&dev->regs->sr, I2C_SR_DB);
189 if (ret < 0)
190 debug("error: device busy after operation\n");
191
192 return old_ret ? old_ret : ret;
193}
194
195static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
196 uint len, const u8 *buf, bool *stop)
197{
198 int ret;
199 const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
200 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
201
202 debug("%s: addr = %x, len = %d\n", __func__, addr, len);
203
204 writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);
205
206 writel(irq_flags, &regs->ie);
207 writel(irq_flags, &regs->ic);
208
209 debug("start condition\n");
210 writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);
211
212 ret = wait_for_irq(dev, irq_flags, stop);
213 if (ret < 0)
214 goto error;
215
216 while (len--) {
217 debug("sending %x\n", *buf);
218 writel(*buf++, &regs->dttx);
219
220 writel(irq_flags, &regs->ic);
221
222 ret = wait_for_irq(dev, irq_flags, stop);
223 if (ret < 0)
224 goto error;
225 }
226
227error:
228 writel(irq_flags, &regs->ic);
229
230 if (*stop)
231 ret = issue_stop(dev, ret);
232
233 return ret;
234}
235
236static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
237 uint len, u8 *buf, bool *stop)
238{
239 int ret = 0;
240 const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
241 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
242
243 debug("%s: addr = %x, len = %d\n", __func__, addr, len);
244
245 /*
246 * In case 'len == 0', only the slave address should be sent
247 * for probing, which is covered by the transmit function.
248 */
249 if (len == 0)
250 return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
251
252 writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);
253
254 writel(0, &regs->rbc);
255 writel(irq_flags, &regs->ie);
256 writel(irq_flags, &regs->ic);
257
258 debug("start condition\n");
259 writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
260 &regs->cr);
261
262 while (len--) {
263 ret = wait_for_irq(dev, irq_flags, stop);
264 if (ret < 0)
265 goto error;
266
267 *buf++ = readl(&regs->dtrx);
268 debug("received %x\n", *(buf - 1));
269
270 if (len == 1)
271 writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);
272
273 writel(irq_flags, &regs->ic);
274 }
275
276error:
277 writel(irq_flags, &regs->ic);
278
279 if (*stop)
280 ret = issue_stop(dev, ret);
281
282 return ret;
283}
284
285static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
286 int nmsgs)
287{
288 int ret;
289 struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
290 bool stop;
291
292 ret = check_device_busy(dev->regs);
293 if (ret < 0)
294 return ret;
295
296 for (; nmsgs > 0; nmsgs--, msg++) {
297 /* If next message is read, skip the stop condition */
298 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
299
300 if (msg->flags & I2C_M_RD)
301 ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
302 msg->buf, &stop);
303 else
304 ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
305 msg->buf, &stop);
306
307 if (ret < 0)
308 break;
309 }
310
311 return ret;
312}
313
314static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
315{
316 int ret;
317 unsigned int clk_count;
318 struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
319 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
320
321 /* max supported frequency is 400 kHz */
322 if (speed > 400000)
323 return -EINVAL;
324
325 ret = check_device_busy(dev->regs);
326 if (ret < 0)
327 return ret;
328
329 /* make sure the bus is idle when changing the frequency */
330 writel(I2C_BRST_RSCLO, &regs->brst);
331
332 clk_count = dev->fioclk / speed;
333
334 writel(clk_count, &regs->cyc);
335 writel(clk_count / 2, &regs->lctl);
336 writel(clk_count / 2, &regs->ssut);
337 writel(clk_count / 16, &regs->dsut);
338
339 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);
340
341 /*
342 * Theoretically, each byte can be transferred in
343 * 1000000 * 9 / speed usec.
344 * This time out value is long enough.
345 */
346 dev->timeout = 100000000L / speed;
347
348 return 0;
349}
350
351static const struct dm_i2c_ops uniphier_fi2c_ops = {
352 .xfer = uniphier_fi2c_xfer,
353 .set_bus_speed = uniphier_fi2c_set_bus_speed,
354};
355
356static const struct udevice_id uniphier_fi2c_of_match[] = {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900357 { .compatible = "socionext,uniphier-fi2c" },
358 { /* sentinel */ }
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900359};
360
361U_BOOT_DRIVER(uniphier_fi2c) = {
362 .name = "uniphier-fi2c",
363 .id = UCLASS_I2C,
364 .of_match = uniphier_fi2c_of_match,
365 .probe = uniphier_fi2c_probe,
366 .remove = uniphier_fi2c_remove,
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900367 .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
368 .ops = &uniphier_fi2c_ops,
369};