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wdenk4e5ca3e2003-12-08 01:34:36 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 *
4 * (C) Copyright 2000
wdenk4e5ca3e2003-12-08 01:34:36 +00005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk4e5ca3e2003-12-08 01:34:36 +00008 */
9
10#include <common.h>
11
TsiChungLiew52b01762007-07-05 23:36:16 -050012#include <asm/timer.h>
13#include <asm/immap.h>
Richard Retanubun42a83762009-03-20 15:30:10 -040014#include <watchdog.h>
wdenk4e5ca3e2003-12-08 01:34:36 +000015
TsiChungLiew99c03c12007-08-05 03:58:52 -050016DECLARE_GLOBAL_DATA_PTR;
17
Richard Retanubun42a83762009-03-20 15:30:10 -040018static volatile ulong timestamp = 0;
19
20#ifndef CONFIG_SYS_WATCHDOG_FREQ
21#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
22#endif
stroesecd42dee2004-12-16 17:56:09 +000023
TsiChung Liew8e585f02007-06-18 13:50:13 -050024#if defined(CONFIG_MCFTMR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#ifndef CONFIG_SYS_UDELAY_BASE
TsiChung Liew8e585f02007-06-18 13:50:13 -050026# error "uDelay base not defined!"
27#endif
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
TsiChung Liew8e585f02007-06-18 13:50:13 -050030# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
31#endif
TsiChungLiew52b01762007-07-05 23:36:16 -050032extern void dtimer_intr_setup(void);
TsiChung Liew8e585f02007-06-18 13:50:13 -050033
Ingo van Lil3eb90ba2009-11-24 14:09:21 +010034void __udelay(unsigned long usec)
TsiChung Liew8e585f02007-06-18 13:50:13 -050035{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050037 uint start, now, tmp;
38
39 while (usec > 0) {
40 if (usec > 65000)
41 tmp = 65000;
42 else
43 tmp = usec;
44 usec = usec - tmp;
45
46 /* Set up TIMER 3 as timebase clock */
47 timerp->tmr = DTIM_DTMR_RST_RST;
48 timerp->tcn = 0;
49 /* set period to 1 us */
50 timerp->tmr =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051 CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
TsiChungLiew52b01762007-07-05 23:36:16 -050052 DTIM_DTMR_RST_EN;
TsiChung Liew8e585f02007-06-18 13:50:13 -050053
54 start = now = timerp->tcn;
55 while (now < start + tmp)
56 now = timerp->tcn;
57 }
58}
59
60void dtimer_interrupt(void *not_used)
61{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050063
64 /* check for timer interrupt asserted */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
TsiChung Liew8e585f02007-06-18 13:50:13 -050066 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
67 timestamp++;
Richard Retanubun42a83762009-03-20 15:30:10 -040068
69 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
70 if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
71 WATCHDOG_RESET ();
72 }
73 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
TsiChung Liew8e585f02007-06-18 13:50:13 -050074 return;
75 }
76}
77
Jason Jin444ddfc2011-08-19 10:02:32 +080078int timer_init(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -050079{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050081
82 timestamp = 0;
83
84 timerp->tcn = 0;
85 timerp->trr = 0;
86
87 /* Set up TIMER 4 as clock */
88 timerp->tmr = DTIM_DTMR_RST_RST;
89
TsiChungLiew52b01762007-07-05 23:36:16 -050090 /* initialize and enable timer interrupt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
TsiChung Liew8e585f02007-06-18 13:50:13 -050092
93 timerp->tcn = 0;
94 timerp->trr = 1000; /* Interrupt every ms */
95
TsiChungLiew52b01762007-07-05 23:36:16 -050096 dtimer_intr_setup();
TsiChung Liew8e585f02007-06-18 13:50:13 -050097
98 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
TsiChung Liew8e585f02007-06-18 13:50:13 -0500100 DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
Jason Jin444ddfc2011-08-19 10:02:32 +0800101
102 return 0;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500103}
104
TsiChung Liew8e585f02007-06-18 13:50:13 -0500105ulong get_timer(ulong base)
106{
107 return (timestamp - base);
108}
109
TsiChung Liew8e585f02007-06-18 13:50:13 -0500110#endif /* CONFIG_MCFTMR */
111
112#if defined(CONFIG_MCFPIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#if !defined(CONFIG_SYS_PIT_BASE)
114# error "CONFIG_SYS_PIT_BASE not defined!"
TsiChung Liew8e585f02007-06-18 13:50:13 -0500115#endif
116
117static unsigned short lastinc;
118
Ingo van Lil3eb90ba2009-11-24 14:09:21 +0100119void __udelay(unsigned long usec)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500120{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500122 uint tmp;
123
124 while (usec > 0) {
125 if (usec > 65000)
126 tmp = 65000;
127 else
128 tmp = usec;
129 usec = usec - tmp;
130
131 /* Set up TIMER 3 as timebase clock */
132 timerp->pcsr = PIT_PCSR_OVW;
133 timerp->pmr = 0;
134 /* set period to 1 us */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500136
137 timerp->pmr = tmp;
138 while (timerp->pcntr > 0) ;
139 }
140}
141
142void timer_init(void)
143{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500145 timestamp = 0;
146
147 /* Set up TIMER 4 as poll clock */
148 timerp->pcsr = PIT_PCSR_OVW;
149 timerp->pmr = lastinc = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
Jason Jin444ddfc2011-08-19 10:02:32 +0800151
152 return 0;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500153}
154
TsiChung Liew8e585f02007-06-18 13:50:13 -0500155ulong get_timer(ulong base)
156{
157 unsigned short now, diff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500159
160 now = timerp->pcntr;
161 diff = -(now - lastinc);
162
163 timestamp += diff;
164 lastinc = now;
165 return timestamp - base;
166}
167
168void wait_ticks(unsigned long ticks)
169{
Graeme Russ5c8404a2011-07-15 02:18:12 +0000170 u32 start = get_timer(0);
171 while (get_timer(start) < ticks) ;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500172}
173#endif /* CONFIG_MCFPIT */
stroesecd42dee2004-12-16 17:56:09 +0000174
wdenk70f05ac2004-06-09 15:24:18 +0000175/*
176 * This function is derived from PowerPC code (read timebase as long long).
177 * On M68K it just returns the timer value.
178 */
179unsigned long long get_ticks(void)
180{
181 return get_timer(0);
182}
183
Stefan Roesef2302d42008-08-06 14:05:38 +0200184unsigned long usec2ticks(unsigned long usec)
185{
186 return get_timer(usec);
187}
188
wdenk70f05ac2004-06-09 15:24:18 +0000189/*
190 * This function is derived from PowerPC code (timebase clock frequency).
191 * On M68K it returns the number of timer ticks per second.
192 */
TsiChungLiew52b01762007-07-05 23:36:16 -0500193ulong get_tbclk(void)
wdenk70f05ac2004-06-09 15:24:18 +0000194{
195 ulong tbclk;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 tbclk = CONFIG_SYS_HZ;
wdenk70f05ac2004-06-09 15:24:18 +0000197 return tbclk;
198}