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Marek Behún2b69a672018-04-24 17:21:30 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell Armada 37xx SoC Watchdog Driver
4 *
5 * Marek Behun <marek.behun@nic.cz>
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <wdt.h>
Simon Glass401d1c42020-10-30 21:38:53 -060011#include <asm/global_data.h>
Marek Behún2b69a672018-04-24 17:21:30 +020012#include <asm/io.h>
13#include <asm/arch/cpu.h>
14#include <asm/arch/soc.h>
Simon Glass336d4612020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Marek Behún2b69a672018-04-24 17:21:30 +020016
17DECLARE_GLOBAL_DATA_PTR;
18
19struct a37xx_wdt {
20 void __iomem *sel_reg;
21 void __iomem *reg;
22 ulong clk_rate;
23 u64 timeout;
24};
25
26/*
Marek Behún7b03e992018-12-17 16:10:06 +010027 * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
Marek Behún2b69a672018-04-24 17:21:30 +020028 */
29
Marek Behún7b03e992018-12-17 16:10:06 +010030#define CNTR_CTRL(id) ((id) * 0x10)
Marek Behún2b69a672018-04-24 17:21:30 +020031#define CNTR_CTRL_ENABLE 0x0001
32#define CNTR_CTRL_ACTIVE 0x0002
33#define CNTR_CTRL_MODE_MASK 0x000c
34#define CNTR_CTRL_MODE_ONESHOT 0x0000
Marek Behún7b03e992018-12-17 16:10:06 +010035#define CNTR_CTRL_MODE_HWSIG 0x000c
36#define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
37#define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
Marek Behún2b69a672018-04-24 17:21:30 +020038#define CNTR_CTRL_PRESCALE_MASK 0xff00
39#define CNTR_CTRL_PRESCALE_MIN 2
40#define CNTR_CTRL_PRESCALE_SHIFT 8
41
Marek Behún7b03e992018-12-17 16:10:06 +010042#define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
43#define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
Marek Behún2b69a672018-04-24 17:21:30 +020044
Marek Behún7b03e992018-12-17 16:10:06 +010045static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val)
Marek Behún2b69a672018-04-24 17:21:30 +020046{
Marek Behún7b03e992018-12-17 16:10:06 +010047 writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id));
48 writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id));
Marek Behún2b69a672018-04-24 17:21:30 +020049}
50
Marek Behún7b03e992018-12-17 16:10:06 +010051static void counter_enable(struct a37xx_wdt *priv, int id)
Marek Behún2b69a672018-04-24 17:21:30 +020052{
Marek Behún7b03e992018-12-17 16:10:06 +010053 setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
Marek Behún2b69a672018-04-24 17:21:30 +020054}
55
Marek Behún7b03e992018-12-17 16:10:06 +010056static void counter_disable(struct a37xx_wdt *priv, int id)
Marek Behún2b69a672018-04-24 17:21:30 +020057{
Marek Behún7b03e992018-12-17 16:10:06 +010058 clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
59}
Marek Behún2b69a672018-04-24 17:21:30 +020060
Pali Rohár65066772022-02-23 14:21:40 +010061static void init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
Marek Behún7b03e992018-12-17 16:10:06 +010062{
63 u32 reg;
64
65 reg = readl(priv->reg + CNTR_CTRL(id));
Marek Behún7b03e992018-12-17 16:10:06 +010066
67 reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
68 CNTR_CTRL_TRIG_SRC_MASK);
69
70 /* set mode */
71 reg |= mode;
72
73 /* set prescaler to the min value */
74 reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
75
76 /* set trigger source */
77 reg |= trig_src;
78
79 writel(reg, priv->reg + CNTR_CTRL(id));
Marek Behún2b69a672018-04-24 17:21:30 +020080}
81
82static int a37xx_wdt_reset(struct udevice *dev)
83{
84 struct a37xx_wdt *priv = dev_get_priv(dev);
85
86 if (!priv->timeout)
87 return -EINVAL;
88
Marek Behún7b03e992018-12-17 16:10:06 +010089 /* counter 1 is retriggered by forcing end count on counter 0 */
90 counter_disable(priv, 0);
91 counter_enable(priv, 0);
Marek Behún2b69a672018-04-24 17:21:30 +020092
93 return 0;
94}
95
96static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)
97{
98 struct a37xx_wdt *priv = dev_get_priv(dev);
99
Marek Behún7b03e992018-12-17 16:10:06 +0100100 /* first we set timeout to 0 */
101 counter_disable(priv, 1);
102 set_counter_value(priv, 1, 0);
103 counter_enable(priv, 1);
104
105 /* and then we start counter 1 by forcing end count on counter 0 */
106 counter_disable(priv, 0);
107 counter_enable(priv, 0);
Marek Behún2b69a672018-04-24 17:21:30 +0200108
109 return 0;
110}
111
112static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
113{
114 struct a37xx_wdt *priv = dev_get_priv(dev);
Marek Behún2b69a672018-04-24 17:21:30 +0200115
Pali Rohár65066772022-02-23 14:21:40 +0100116 init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
117 init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG, CNTR_CTRL_TRIG_SRC_PREV_CNTR);
Marek Behún2b69a672018-04-24 17:21:30 +0200118
119 priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
120
Marek Behún7b03e992018-12-17 16:10:06 +0100121 set_counter_value(priv, 0, 0);
122 set_counter_value(priv, 1, priv->timeout);
123 counter_enable(priv, 1);
Marek Behún2b69a672018-04-24 17:21:30 +0200124
Marek Behún7b03e992018-12-17 16:10:06 +0100125 /* we have to force end count on counter 0 to start counter 1 */
126 counter_enable(priv, 0);
Marek Behún2b69a672018-04-24 17:21:30 +0200127
128 return 0;
129}
130
131static int a37xx_wdt_stop(struct udevice *dev)
132{
133 struct a37xx_wdt *priv = dev_get_priv(dev);
134
Marek Behún7b03e992018-12-17 16:10:06 +0100135 counter_disable(priv, 1);
136 counter_disable(priv, 0);
137 writel(0, priv->sel_reg);
Marek Behún2b69a672018-04-24 17:21:30 +0200138
139 return 0;
140}
141
142static int a37xx_wdt_probe(struct udevice *dev)
143{
144 struct a37xx_wdt *priv = dev_get_priv(dev);
145 fdt_addr_t addr;
146
Pali Rohár0c4625a2022-02-14 11:34:25 +0100147 priv->sel_reg = (void __iomem *)MVEBU_REGISTER(0x0d064);
Marek Behún2b69a672018-04-24 17:21:30 +0200148
Pali Rohár0c4625a2022-02-14 11:34:25 +0100149 addr = dev_read_addr(dev);
Marek Behún2b69a672018-04-24 17:21:30 +0200150 if (addr == FDT_ADDR_T_NONE)
151 goto err;
152 priv->reg = (void __iomem *)addr;
153
154 priv->clk_rate = (ulong)get_ref_clk() * 1000000;
155
Marek Behún2b69a672018-04-24 17:21:30 +0200156 /*
Marek Behún7b03e992018-12-17 16:10:06 +0100157 * We use counter 1 as watchdog timer, therefore we only set bit
158 * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on
159 * counter 1.
Marek Behún2b69a672018-04-24 17:21:30 +0200160 */
161 writel(1 << 1, priv->sel_reg);
162
163 return 0;
164err:
165 dev_err(dev, "no io address\n");
166 return -ENODEV;
167}
168
169static const struct wdt_ops a37xx_wdt_ops = {
170 .start = a37xx_wdt_start,
171 .reset = a37xx_wdt_reset,
172 .stop = a37xx_wdt_stop,
173 .expire_now = a37xx_wdt_expire_now,
174};
175
176static const struct udevice_id a37xx_wdt_ids[] = {
177 { .compatible = "marvell,armada-3700-wdt" },
178 {}
179};
180
181U_BOOT_DRIVER(a37xx_wdt) = {
182 .name = "armada_37xx_wdt",
183 .id = UCLASS_WDT,
184 .of_match = a37xx_wdt_ids,
185 .probe = a37xx_wdt_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700186 .priv_auto = sizeof(struct a37xx_wdt),
Marek Behún2b69a672018-04-24 17:21:30 +0200187 .ops = &a37xx_wdt_ops,
188};