blob: 47fc7c04bdb6ed602d73879ee788403fdcdde2ef [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2004
3 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4 *
5 * Eric Schumann, Phytec Messtechnik
6 * adapted for mt46v32m16-75 DDR-RAM
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Jon Smirlc9969942009-06-14 18:21:28 -04009 */
10
11#define SDRAM_DDR 1 /* is DDR */
12
13/* Settings for XLB = 132 MHz */
14
15#define SDRAM_MODE 0x018D0000
16#define SDRAM_EMODE 0x40090000
17#define SDRAM_CONTROL 0x71500F00
18#define SDRAM_CONFIG1 0x73711930
19#define SDRAM_CONFIG2 0x47770000
20
21#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */