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wdenk3bbc8992003-12-07 22:27:15 +00001/*
2 * (C) Copyright 2003
3 * MuLogic B.V.
4 *
5 * (C) Copyright 2002
6 * Simple Network Magic Corporation
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenk3bbc8992003-12-07 22:27:15 +000012 */
13
14/*
15 * board/config.h - configuration options, board specific
16 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/* various debug settings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */
wdenk3bbc8992003-12-07 22:27:15 +000023#undef CONFIG_SILENT_CONSOLE /* silent console */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */
wdenk3bbc8992003-12-07 22:27:15 +000025#undef DEBUG_FLASH /* debug flash code */
26#undef FLASH_DEBUG /* debug fash code */
27#undef DEBUG_ENV /* debug environment code */
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
wdenk3bbc8992003-12-07 22:27:15 +000030#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_QS850 1 /* ...on a QS850 module */
38#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xFFF00000
41
wdenk3bbc8992003-12-07 22:27:15 +000042/* Select the target clock speed */
43#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
44#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
45#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */
46#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */
47#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */
48
49#ifdef CONFIG_CLOCK_16MHZ
50#define CONFIG_CLOCK_MULT 512
51#endif
52
53#ifdef CONFIG_CLOCK_33MHZ
54#define CONFIG_CLOCK_MULT 1024
55#endif
56
57#ifdef CONFIG_CLOCK_50MHZ
58#define CONFIG_CLOCK_MULT 1525
59#endif
60
61#ifdef CONFIG_CLOCK_66MHZ
62#define CONFIG_CLOCK_MULT 2048
63#endif
64
65#ifdef CONFIG_CLOCK_80MHZ
66#define CONFIG_CLOCK_MULT 2441
67#endif
68
69/* choose flash size, 4Mb or 8Mb */
70#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */
71#undef CONFIG_FLASH_8MB /* board has 8Mb flash */
72
73#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */
74
75#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
76#undef CONFIG_8xx_CONS_SMC2
77#undef CONFIG_8xx_CONS_NONE
78
79#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
80
81#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
82
83/* Define default IP addresses */
84#define CONFIG_IPADDR 192.168.1.99 /* own ip address */
85#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */
86
87/* message to say directly after booting */
88#define CONFIG_PREBOOT "echo '';" \
89 "echo 'type:';" \
90 "echo 'run boot_nfs to boot to NFS';" \
91 "echo 'run boot_flash to boot to flash';" \
92 "echo '';" \
93 "echo 'run flash_rootfs to install a new rootfs';" \
94 "echo 'run flash_env to clear the env sector';" \
95 "echo 'run flash_rw to clear the rw fs';" \
96 "echo 'run flash_uboot to install a new u-boot';" \
97 "echo 'run flash_kernel to install a new kernel';"
98
99/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
100#define CONFIG_BOOTDELAY 5
101#define CONFIG_BOOTCOMMAND "run boot_nfs"
102
103#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */
104
105/* Our flash filesystem looks like this
106 *
107 * 4Mb board:
108 * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb)
109 * ffec 0000 - ffed ffff read-write filesystem (ext2)
110 * ffee 0000 - ffef ffff environment
111 * fff0 0000 - fff1 ffff u-boot
112 * fff2 0000 - ffff ffff linux kernel
113 *
114 * 8Mb board:
115 * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb)
116 * ffec 0000 - ffed ffff read-write filesystem (ext2)
117 * ffee 0000 - ffef ffff environment
118 * fff0 0000 - fff1 ffff u-boot
119 * fff2 0000 - ffff ffff linux kernel
120 *
121 */
122
123/* environment for 4Mb board */
124#ifdef CONFIG_FLASH_4MB
125#define CONFIG_EXTRA_ENV_SETTINGS \
126 "serial#=QS850\0" \
127 "hostname=qs850\0" \
128 "netdev=eth0\0" \
129 "ethaddr=00:01:02:B4:36:56\0" \
130 "rootpath=/exports/rootfs\0" \
131 "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
132 /* fill in variables */ \
133 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
134 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
135 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
136 /* commands */ \
137 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
138 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
139 /* reinstall flash parts */ \
140 "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
141 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
142 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
143 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
144 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
145#endif /* CONFIG_FLASH_4MB */
146
147/* environment for 8Mb board */
148#ifdef CONFIG_FLASH_8MB
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "serial#=QS850\0" \
151 "hostname=qs850\0" \
152 "netdev=eth0\0" \
153 "ethaddr=00:01:02:B4:36:56\0" \
154 "rootpath=/exports/rootfs\0" \
155 "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
156 /* fill in variables */ \
157 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
158 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
159 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
160 /* commands */ \
161 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
162 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
163 /* reinstall flash parts */ \
164 "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
165 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
166 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
167 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
168 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
169#endif /* CONFIG_FLASH_8MB */
170
171#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk3bbc8992003-12-07 22:27:15 +0000173#undef CONFIG_WATCHDOG /* watchdog disabled */
174#undef CONFIG_STATUS_LED /* Status LED disabled */
175#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
176
Jon Loeliger18225e82007-07-09 21:31:24 -0500177/*
178 * BOOTP options
179 */
180#define CONFIG_BOOTP_SUBNETMASK
181#define CONFIG_BOOTP_GATEWAY
182#define CONFIG_BOOTP_HOSTNAME
183#define CONFIG_BOOTP_BOOTPATH
184#define CONFIG_BOOTP_BOOTFILESIZE
wdenk3bbc8992003-12-07 22:27:15 +0000185
186#undef CONFIG_MAC_PARTITION
187#undef CONFIG_DOS_PARTITION
188
189#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
190
wdenk3bbc8992003-12-07 22:27:15 +0000191
Jon Loeliger12aa9fd2007-07-08 14:55:07 -0500192/*
193 * Command line configuration.
194 */
195
196#define CONFIG_CMD_BDI
197#define CONFIG_CMD_BOOTD
198#define CONFIG_CMD_CONSOLE
199#define CONFIG_CMD_DATE
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500200#define CONFIG_CMD_SAVEENV
Jon Loeliger12aa9fd2007-07-08 14:55:07 -0500201#define CONFIG_CMD_FLASH
202#define CONFIG_CMD_IMI
203#define CONFIG_CMD_IMMAP
204#define CONFIG_CMD_MEMORY
205#define CONFIG_CMD_NET
206#define CONFIG_CMD_RUN
207
wdenk3bbc8992003-12-07 22:27:15 +0000208
209/*-----------------------------------------------------------------------
210 * Environment variable storage is in FLASH, one sector before U-boot
211 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200212#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200213#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */
214#define CONFIG_ENV_SIZE 0x2000 /* 8kb */
215#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */
wdenk3bbc8992003-12-07 22:27:15 +0000216
217/*-----------------------------------------------------------------------
218 * Miscellaneous configurable options
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk3bbc8992003-12-07 22:27:15 +0000221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenk3bbc8992003-12-07 22:27:15 +0000223
Jon Loeliger12aa9fd2007-07-08 14:55:07 -0500224#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk3bbc8992003-12-07 22:27:15 +0000226#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk3bbc8992003-12-07 22:27:15 +0000228#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
230#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
231#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk3bbc8992003-12-07 22:27:15 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */
234#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk3bbc8992003-12-07 22:27:15 +0000235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
wdenk3bbc8992003-12-07 22:27:15 +0000237
wdenk3bbc8992003-12-07 22:27:15 +0000238/*-----------------------------------------------------------------------
239 * Low Level Configuration Settings
240 * (address mappings, register initial values, etc.)
241 * You should know what you are doing if you make changes here.
242 */
243
244/*-----------------------------------------------------------------------
245 * Internal Memory Mapped Register
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_IMMR 0xFF000000
wdenk3bbc8992003-12-07 22:27:15 +0000248
249/*-----------------------------------------------------------------------
250 * Definitions for initial stack pointer and data area (in DPRAM)
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200253#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200254#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk3bbc8992003-12-07 22:27:15 +0000256
257/*-----------------------------------------------------------------------
258 * Start addresses for the final memory configuration
259 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk3bbc8992003-12-07 22:27:15 +0000261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SDRAM_BASE 0x00000000
263#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */
wdenk3bbc8992003-12-07 22:27:15 +0000264
265#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */
266#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */
267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
269#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */
270#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk3bbc8992003-12-07 22:27:15 +0000271
272/*
273 * For booting Linux, the board info and command line data
274 * have to be in the first 8 MB of memory, since this is
275 * the maximum mapped by the Linux kernel during initialization.
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk3bbc8992003-12-07 22:27:15 +0000278
279/*-----------------------------------------------------------------------
280 * TODO flash parameters
281 * FLASH organization for Intel Strataflash
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */
284#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
285#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk3bbc8992003-12-07 22:27:15 +0000286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
288#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk3bbc8992003-12-07 22:27:15 +0000289
290/*-----------------------------------------------------------------------
291 * Cache Configuration
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger12aa9fd2007-07-08 14:55:07 -0500294#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk3bbc8992003-12-07 22:27:15 +0000296#endif
297
298/*-----------------------------------------------------------------------
299 * SYPCR - System Protection Control 11-9
300 * SYPCR can only be written once after reset!
301 *-----------------------------------------------------------------------
302 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
303 */
304
305#ifdef CONFIG_WATCHDOG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
wdenk3bbc8992003-12-07 22:27:15 +0000307#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
wdenk3bbc8992003-12-07 22:27:15 +0000309#endif
310
311/*-----------------------------------------------------------------------
312 * SIUMCR - SIU Module Configuration 11-6
313 *-----------------------------------------------------------------------
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
wdenk3bbc8992003-12-07 22:27:15 +0000316
317/*-----------------------------------------------------------------------
318 * TBSCR - Time Base Status and Control 11-26
319 *-----------------------------------------------------------------------
320 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk3bbc8992003-12-07 22:27:15 +0000322
323/*-----------------------------------------------------------------------
324 * RTCSC - Real-Time Clock Status and Control Register 11-27
325 *-----------------------------------------------------------------------
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk3bbc8992003-12-07 22:27:15 +0000328
329/*-----------------------------------------------------------------------
330 * PISCR - Periodic Interrupt Status and Control 11-31
331 *-----------------------------------------------------------------------
332 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk3bbc8992003-12-07 22:27:15 +0000334
335/*-----------------------------------------------------------------------
336 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
337 *-----------------------------------------------------------------------
338 */
339
340/* MF (Multiplication Factor of SPLL) */
341/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
342#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
wdenk3bbc8992003-12-07 22:27:15 +0000344
345/*-----------------------------------------------------------------------
346 * SCCR - System Clock and reset Control Register 15-27
347 *-----------------------------------------------------------------------
348 */
349#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
351#define CONFIG_SYS_BRGCLK_PRESCALE 1
wdenk3bbc8992003-12-07 22:27:15 +0000352#endif
353
354#if defined(CONFIG_CLOCK_66MHZ)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
356#define CONFIG_SYS_BRGCLK_PRESCALE 4
wdenk3bbc8992003-12-07 22:27:15 +0000357#endif
358
359#if defined(CONFIG_CLOCK_80MHZ)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
361#define CONFIG_SYS_BRGCLK_PRESCALE 4
wdenk3bbc8992003-12-07 22:27:15 +0000362#endif
363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define SCCR_MASK CONFIG_SYS_SCCR
wdenk3bbc8992003-12-07 22:27:15 +0000365
366/*-----------------------------------------------------------------------
367 * Debug Enable Register
368 * 0x73E67C0F - All interrupts handled by BDM
369 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
370 *-----------------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_DER 0x73E67C0F
372#define CONFIG_SYS_DER 0x0082400F
wdenk3bbc8992003-12-07 22:27:15 +0000373
374 #-------------------------------------------------------------------------
375 # Program the Debug Enable Register (DER). This register provides the user
376 # with the reason for entering into the debug mode. We want all conditions
377 # to end up as an exception. We don't want to enter into debug mode for
378 # any condition. See the back of of the Development Support section of the
379 # MPC860 User Manual for a description of this register.
380 #-------------------------------------------------------------------------
381*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_DER 0
wdenk3bbc8992003-12-07 22:27:15 +0000383
384/*-----------------------------------------------------------------------
385 * Memory Controller Initialization Constants
386 *-----------------------------------------------------------------------
387 */
388
389/*
390 * BR0 and OR0 (AMD dual FLASH devices)
391 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
392 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_PRELIM_OR_AM
394#define CONFIG_SYS_OR_TIMING_FLASH
wdenk3bbc8992003-12-07 22:27:15 +0000395
396/*
397 *-----------------------------------------------------------------------
398 * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
399 * flash that resides on the QS850.
400 *-----------------------------------------------------------------------
401 */
402
403/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
404/* represents a minumum 32K block size. */
405#define vBR0_BA ((0xFF80 << 16) + (0 << 15))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V)
wdenk3bbc8992003-12-07 22:27:15 +0000407
408/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */
409/* which defines a 8 Mbyte memory block. */
410#define vOR0_AM ((0xFF80 << 16) + (0 << 15))
411
412#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
413/* 0101 = Add a 5 clock cycle wait state */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
wdenk3bbc8992003-12-07 22:27:15 +0000415#endif
416
417#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
418/* 0011 = Add a 3 clock cycle wait state */
419/* 29.8ns clock * (3 + 2) = 149ns cycle time */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
wdenk3bbc8992003-12-07 22:27:15 +0000421#endif
422
423#if defined(CONFIG_CLOCK_16MHZ)
424/* 0010 = Add a 2 clock cycle wait state */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
wdenk3bbc8992003-12-07 22:27:15 +0000426#endif
427
428/*
429 * BR1 and OR1 (SDRAM)
430 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
431 * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
432 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
433 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
434 */
435
436#define SDRAM_BASE 0x00000000 /* SDRAM bank */
437#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
438
439/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
440 * represents a 128 Mbyte block the DRAM in
441 * this address base.
442 */
443#define vOR1_AM ((0xF800 << 16) + (0 << 15))
444#define vBR1_BA ((0x0000 << 16) + (0 << 15))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
446#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
wdenk3bbc8992003-12-07 22:27:15 +0000447
448/* Machine A Mode Register */
449
450/* PTA Periodic Timer A */
451
452#if defined(CONFIG_CLOCK_80MHZ)
453#define vMAMR_PTA (19 << 24)
454#endif
455
456#if defined(CONFIG_CLOCK_66MHZ)
457#define vMAMR_PTA (16 << 24)
458#endif
459
460#if defined(CONFIG_CLOCK_50MHZ)
461#define vMAMR_PTA (195 << 24)
462#endif
463
464#if defined(CONFIG_CLOCK_33MHZ)
465#define vMAMR_PTA (131 << 24)
466#endif
467
468#if defined(CONFIG_CLOCK_16MHZ)
469#define vMAMR_PTA (65 << 24)
470#endif
471
472/* For boards with 16M of SDRAM */
473#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
wdenk3bbc8992003-12-07 22:27:15 +0000475MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
476
477/* For boards with 32M of SDRAM */
478#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
wdenk3bbc8992003-12-07 22:27:15 +0000480MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
481
482
483/* Memory Periodic Timer Prescaler Register */
484
485#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
486/* Divide by 32 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_MPTPR 0x02
wdenk3bbc8992003-12-07 22:27:15 +0000488#endif
489
490#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
491/* Divide by 16 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_MPTPR 0x04
wdenk3bbc8992003-12-07 22:27:15 +0000493#endif
494
495/*
496 * BR2 and OR2 (Unused)
497 * Base address = 0xF020_0000 - 0xF020_0FFF
498 *
499 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_OR2_PRELIM 0xFFF00000
501#define CONFIG_SYS_BR2_PRELIM 0xF0200000
wdenk3bbc8992003-12-07 22:27:15 +0000502
503/*
504 * BR3 and OR3 (External Bus CS3)
505 * Base address = 0xF030_0000 - 0xF030_0FFF
506 *
507 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_OR3_PRELIM 0xFFF00000
509#define CONFIG_SYS_BR3_PRELIM 0xF0300000
wdenk3bbc8992003-12-07 22:27:15 +0000510
511/*
512 * BR4 and OR4 (External Bus CS3)
513 * Base address = 0xF040_0000 - 0xF040_0FFF
514 *
515 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_OR4_PRELIM 0xFFF00000
517#define CONFIG_SYS_BR4_PRELIM 0xF0400000
wdenk3bbc8992003-12-07 22:27:15 +0000518
519
520/*
521 * BR4 and OR4 (External Bus CS3)
522 * Base address = 0xF050_0000 - 0xF050_0FFF
523 *
524 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_OR5_PRELIM 0xFFF00000
526#define CONFIG_SYS_BR5_PRELIM 0xF0500000
wdenk3bbc8992003-12-07 22:27:15 +0000527
528/*
529 * BR6 and OR6 (Unused)
530 * Base address = 0xF060_0000 - 0xF060_0FFF
531 *
532 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_OR6_PRELIM 0xFFF00000
534#define CONFIG_SYS_BR6_PRELIM 0xF0600000
wdenk3bbc8992003-12-07 22:27:15 +0000535
536/*
537 * BR7 and OR7 (Unused)
538 * Base address = 0xF070_0000 - 0xF070_0FFF
539 *
540 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_OR7_PRELIM 0xFFF00000
542#define CONFIG_SYS_BR7_PRELIM 0xF0700000
wdenk3bbc8992003-12-07 22:27:15 +0000543
544/*
wdenk3bbc8992003-12-07 22:27:15 +0000545 * Sanity checks
546 */
547#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
548#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
549#endif
550
551#endif /* __CONFIG_H */