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Dirk Behme53736ba2010-12-11 11:01:00 -05001/*
2 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
3 *
4 * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
5 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 *
7 * Copyright (C) 2007 Atmel Corporation
8 *
9 * Parts taken from linux/drivers/spi/omap2_mcspi.c
10 * Copyright (C) 2005, 2006 Nokia Corporation
11 *
12 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
13 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Dirk Behme53736ba2010-12-11 11:01:00 -050015 */
16
17#include <common.h>
18#include <spi.h>
19#include <malloc.h>
20#include <asm/io.h>
21#include "omap3_spi.h"
22
Nikita Kiryanov54a759c2013-10-16 17:23:24 +030023#define SPI_WAIT_TIMEOUT 3000000
Dirk Behme53736ba2010-12-11 11:01:00 -050024
25static void spi_reset(struct omap3_spi_slave *ds)
26{
27 unsigned int tmp;
28
29 writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &ds->regs->sysconfig);
30 do {
31 tmp = readl(&ds->regs->sysstatus);
32 } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
33
34 writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
35 OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
36 OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
37 &ds->regs->sysconfig);
38
39 writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
40}
41
ajoycc1182b2012-11-17 21:10:15 +000042static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
43{
44 writel(val, &ds->regs->channel[ds->slave.cs].chconf);
45 /* Flash post writes to make immediate effect */
46 readl(&ds->regs->channel[ds->slave.cs].chconf);
47}
48
49static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable)
50{
51 writel(enable, &ds->regs->channel[ds->slave.cs].chctrl);
Wolfgang Denk93e14592013-10-04 17:43:24 +020052 /* Flash post writes to make immediate effect */
ajoycc1182b2012-11-17 21:10:15 +000053 readl(&ds->regs->channel[ds->slave.cs].chctrl);
54}
55
Dirk Behme53736ba2010-12-11 11:01:00 -050056void spi_init()
57{
58 /* do nothing */
59}
60
61struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
62 unsigned int max_hz, unsigned int mode)
63{
64 struct omap3_spi_slave *ds;
Simon Glassd3504fe2013-03-18 19:23:40 +000065 struct mcspi *regs;
Dirk Behme53736ba2010-12-11 11:01:00 -050066
67 /*
68 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
69 * with different number of chip selects (CS, channels):
70 * McSPI1 has 4 CS (bus 0, cs 0 - 3)
71 * McSPI2 has 2 CS (bus 1, cs 0 - 1)
72 * McSPI3 has 2 CS (bus 2, cs 0 - 1)
73 * McSPI4 has 1 CS (bus 3, cs 0)
74 */
75
76 switch (bus) {
77 case 0:
Simon Glassd3504fe2013-03-18 19:23:40 +000078 regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
Dirk Behme53736ba2010-12-11 11:01:00 -050079 break;
Tom Rini4c0620b2012-08-08 14:29:51 -070080#ifdef OMAP3_MCSPI2_BASE
Dirk Behme53736ba2010-12-11 11:01:00 -050081 case 1:
Simon Glassd3504fe2013-03-18 19:23:40 +000082 regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
Dirk Behme53736ba2010-12-11 11:01:00 -050083 break;
Tom Rini4c0620b2012-08-08 14:29:51 -070084#endif
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020085#ifdef OMAP3_MCSPI3_BASE
Dirk Behme53736ba2010-12-11 11:01:00 -050086 case 2:
Simon Glassd3504fe2013-03-18 19:23:40 +000087 regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
Dirk Behme53736ba2010-12-11 11:01:00 -050088 break;
Tom Rini4c0620b2012-08-08 14:29:51 -070089#endif
90#ifdef OMAP3_MCSPI4_BASE
Dirk Behme53736ba2010-12-11 11:01:00 -050091 case 3:
Simon Glassd3504fe2013-03-18 19:23:40 +000092 regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
Dirk Behme53736ba2010-12-11 11:01:00 -050093 break;
Tom Rini4c0620b2012-08-08 14:29:51 -070094#endif
Dirk Behme53736ba2010-12-11 11:01:00 -050095 default:
96 printf("SPI error: unsupported bus %i. \
97 Supported busses 0 - 3\n", bus);
98 return NULL;
99 }
Dirk Behme53736ba2010-12-11 11:01:00 -0500100
101 if (((bus == 0) && (cs > 3)) ||
102 ((bus == 1) && (cs > 1)) ||
103 ((bus == 2) && (cs > 1)) ||
104 ((bus == 3) && (cs > 0))) {
105 printf("SPI error: unsupported chip select %i \
106 on bus %i\n", cs, bus);
107 return NULL;
108 }
Dirk Behme53736ba2010-12-11 11:01:00 -0500109
110 if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
111 printf("SPI error: unsupported frequency %i Hz. \
112 Max frequency is 48 Mhz\n", max_hz);
113 return NULL;
114 }
Dirk Behme53736ba2010-12-11 11:01:00 -0500115
116 if (mode > SPI_MODE_3) {
117 printf("SPI error: unsupported SPI mode %i\n", mode);
118 return NULL;
119 }
Simon Glassd3504fe2013-03-18 19:23:40 +0000120
121 ds = spi_alloc_slave(struct omap3_spi_slave, bus, cs);
122 if (!ds) {
123 printf("SPI error: malloc of SPI structure failed\n");
124 return NULL;
125 }
126
127 ds->regs = regs;
128 ds->freq = max_hz;
Dirk Behme53736ba2010-12-11 11:01:00 -0500129 ds->mode = mode;
130
131 return &ds->slave;
132}
133
134void spi_free_slave(struct spi_slave *slave)
135{
136 struct omap3_spi_slave *ds = to_omap3_spi(slave);
137
138 free(ds);
139}
140
141int spi_claim_bus(struct spi_slave *slave)
142{
143 struct omap3_spi_slave *ds = to_omap3_spi(slave);
144 unsigned int conf, div = 0;
145
146 /* McSPI global module configuration */
147
148 /*
149 * setup when switching from (reset default) slave mode
150 * to single-channel master mode
151 */
152 spi_reset(ds);
153 conf = readl(&ds->regs->modulctrl);
154 conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
155 conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
156 writel(conf, &ds->regs->modulctrl);
157
158 /* McSPI individual channel configuration */
159
160 /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
161 if (ds->freq) {
162 while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
163 > ds->freq)
164 div++;
165 } else
166 div = 0xC;
167
168 conf = readl(&ds->regs->channel[ds->slave.cs].chconf);
169
170 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
171 * REVISIT: this controller could support SPI_3WIRE mode.
172 */
Peter Korsgaard22cbeed2012-10-17 09:20:46 +0000173#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
Tom Rinia4a99ff2012-08-08 14:35:55 -0700174 /*
Peter Korsgaard22cbeed2012-10-17 09:20:46 +0000175 * Some boards have D0 wired as MOSI / D1 as MISO instead of
176 * The normal D0 as MISO / D1 as MOSI.
Tom Rinia4a99ff2012-08-08 14:35:55 -0700177 */
Peter Korsgaard22cbeed2012-10-17 09:20:46 +0000178 conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
179 conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
Tom Rinia4a99ff2012-08-08 14:35:55 -0700180#else
Dirk Behme53736ba2010-12-11 11:01:00 -0500181 conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
182 conf |= OMAP3_MCSPI_CHCONF_DPE0;
Tom Rinia4a99ff2012-08-08 14:35:55 -0700183#endif
Dirk Behme53736ba2010-12-11 11:01:00 -0500184
185 /* wordlength */
186 conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300187 conf |= (ds->slave.wordlen - 1) << 7;
Dirk Behme53736ba2010-12-11 11:01:00 -0500188
189 /* set chipselect polarity; manage with FORCE */
190 if (!(ds->mode & SPI_CS_HIGH))
191 conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
192 else
193 conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
194
195 /* set clock divisor */
196 conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
197 conf |= div << 2;
198
199 /* set SPI mode 0..3 */
200 if (ds->mode & SPI_CPOL)
201 conf |= OMAP3_MCSPI_CHCONF_POL;
202 else
203 conf &= ~OMAP3_MCSPI_CHCONF_POL;
204 if (ds->mode & SPI_CPHA)
205 conf |= OMAP3_MCSPI_CHCONF_PHA;
206 else
207 conf &= ~OMAP3_MCSPI_CHCONF_PHA;
208
209 /* Transmit & receive mode */
210 conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
211
ajoycc1182b2012-11-17 21:10:15 +0000212 omap3_spi_write_chconf(ds,conf);
Dirk Behme53736ba2010-12-11 11:01:00 -0500213
214 return 0;
215}
216
217void spi_release_bus(struct spi_slave *slave)
218{
219 struct omap3_spi_slave *ds = to_omap3_spi(slave);
220
221 /* Reset the SPI hardware */
222 spi_reset(ds);
223}
224
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300225int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
Dirk Behme53736ba2010-12-11 11:01:00 -0500226 unsigned long flags)
227{
228 struct omap3_spi_slave *ds = to_omap3_spi(slave);
229 int i;
230 int timeout = SPI_WAIT_TIMEOUT;
231 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
232
ajoycc1182b2012-11-17 21:10:15 +0000233 /* Enable the channel */
234 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
Dirk Behme53736ba2010-12-11 11:01:00 -0500235
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300236 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
237 chconf |= (ds->slave.wordlen - 1) << 7;
Dirk Behme53736ba2010-12-11 11:01:00 -0500238 chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
239 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000240 omap3_spi_write_chconf(ds,chconf);
Dirk Behme53736ba2010-12-11 11:01:00 -0500241
242 for (i = 0; i < len; i++) {
243 /* wait till TX register is empty (TXS == 1) */
244 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
245 OMAP3_MCSPI_CHSTAT_TXS)) {
246 if (--timeout <= 0) {
247 printf("SPI TXS timed out, status=0x%08x\n",
248 readl(&ds->regs->channel[ds->slave.cs].chstat));
249 return -1;
250 }
251 }
252 /* Write the data */
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300253 unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
254 if (ds->slave.wordlen > 16)
255 writel(((u32 *)txp)[i], tx);
256 else if (ds->slave.wordlen > 8)
257 writel(((u16 *)txp)[i], tx);
258 else
259 writel(((u8 *)txp)[i], tx);
Dirk Behme53736ba2010-12-11 11:01:00 -0500260 }
261
Wolfgang Denk93e14592013-10-04 17:43:24 +0200262 /* wait to finish of transfer */
Vasili Galkace6889a2014-03-09 15:56:52 +0200263 while ((readl(&ds->regs->channel[ds->slave.cs].chstat) &
264 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
265 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS));
ajoycc1182b2012-11-17 21:10:15 +0000266
267 /* Disable the channel otherwise the next immediate RX will get affected */
268 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
269
Dirk Behme53736ba2010-12-11 11:01:00 -0500270 if (flags & SPI_XFER_END) {
Dirk Behme53736ba2010-12-11 11:01:00 -0500271
272 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000273 omap3_spi_write_chconf(ds,chconf);
Dirk Behme53736ba2010-12-11 11:01:00 -0500274 }
275 return 0;
276}
277
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300278int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
Dirk Behme53736ba2010-12-11 11:01:00 -0500279 unsigned long flags)
280{
281 struct omap3_spi_slave *ds = to_omap3_spi(slave);
282 int i;
283 int timeout = SPI_WAIT_TIMEOUT;
284 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
285
ajoycc1182b2012-11-17 21:10:15 +0000286 /* Enable the channel */
287 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
Dirk Behme53736ba2010-12-11 11:01:00 -0500288
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300289 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
290 chconf |= (ds->slave.wordlen - 1) << 7;
Dirk Behme53736ba2010-12-11 11:01:00 -0500291 chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
292 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000293 omap3_spi_write_chconf(ds,chconf);
Dirk Behme53736ba2010-12-11 11:01:00 -0500294
295 writel(0, &ds->regs->channel[ds->slave.cs].tx);
296
297 for (i = 0; i < len; i++) {
298 /* Wait till RX register contains data (RXS == 1) */
299 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
300 OMAP3_MCSPI_CHSTAT_RXS)) {
301 if (--timeout <= 0) {
302 printf("SPI RXS timed out, status=0x%08x\n",
303 readl(&ds->regs->channel[ds->slave.cs].chstat));
304 return -1;
305 }
306 }
ajoycc1182b2012-11-17 21:10:15 +0000307
308 /* Disable the channel to prevent furher receiving */
309 if(i == (len - 1))
310 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
311
Dirk Behme53736ba2010-12-11 11:01:00 -0500312 /* Read the data */
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300313 unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
314 if (ds->slave.wordlen > 16)
315 ((u32 *)rxp)[i] = readl(rx);
316 else if (ds->slave.wordlen > 8)
317 ((u16 *)rxp)[i] = (u16)readl(rx);
318 else
319 ((u8 *)rxp)[i] = (u8)readl(rx);
Dirk Behme53736ba2010-12-11 11:01:00 -0500320 }
321
322 if (flags & SPI_XFER_END) {
323 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000324 omap3_spi_write_chconf(ds,chconf);
Dirk Behme53736ba2010-12-11 11:01:00 -0500325 }
326
327 return 0;
328}
329
jacopo mondi08b5ab02011-03-02 05:13:22 +0000330/*McSPI Transmit Receive Mode*/
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300331int omap3_spi_txrx(struct spi_slave *slave, unsigned int len,
332 const void *txp, void *rxp, unsigned long flags)
jacopo mondi08b5ab02011-03-02 05:13:22 +0000333{
334 struct omap3_spi_slave *ds = to_omap3_spi(slave);
335 int timeout = SPI_WAIT_TIMEOUT;
336 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
337 int irqstatus = readl(&ds->regs->irqstatus);
338 int i=0;
339
340 /*Enable SPI channel*/
ajoycc1182b2012-11-17 21:10:15 +0000341 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000342
343 /*set TRANSMIT-RECEIVE Mode*/
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300344 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
345 chconf |= (ds->slave.wordlen - 1) << 7;
jacopo mondi08b5ab02011-03-02 05:13:22 +0000346 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000347 omap3_spi_write_chconf(ds,chconf);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000348
349 /*Shift in and out 1 byte at time*/
350 for (i=0; i < len; i++){
351 /* Write: wait for TX empty (TXS == 1)*/
352 irqstatus |= (1<< (4*(ds->slave.bus)));
353 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
354 OMAP3_MCSPI_CHSTAT_TXS)) {
355 if (--timeout <= 0) {
356 printf("SPI TXS timed out, status=0x%08x\n",
357 readl(&ds->regs->channel[ds->slave.cs].chstat));
358 return -1;
359 }
360 }
361 /* Write the data */
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300362 unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
363 if (ds->slave.wordlen > 16)
364 writel(((u32 *)txp)[i], tx);
365 else if (ds->slave.wordlen > 8)
366 writel(((u16 *)txp)[i], tx);
367 else
368 writel(((u8 *)txp)[i], tx);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000369
370 /*Read: wait for RX containing data (RXS == 1)*/
371 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
372 OMAP3_MCSPI_CHSTAT_RXS)) {
373 if (--timeout <= 0) {
374 printf("SPI RXS timed out, status=0x%08x\n",
375 readl(&ds->regs->channel[ds->slave.cs].chstat));
376 return -1;
377 }
378 }
379 /* Read the data */
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300380 unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
381 if (ds->slave.wordlen > 16)
382 ((u32 *)rxp)[i] = readl(rx);
383 else if (ds->slave.wordlen > 8)
384 ((u16 *)rxp)[i] = (u16)readl(rx);
385 else
386 ((u8 *)rxp)[i] = (u8)readl(rx);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000387 }
ajoycc1182b2012-11-17 21:10:15 +0000388 /* Disable the channel */
Wolfgang Denk93e14592013-10-04 17:43:24 +0200389 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000390
391 /*if transfer must be terminated disable the channel*/
392 if (flags & SPI_XFER_END) {
393 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000394 omap3_spi_write_chconf(ds,chconf);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000395 }
396
397 return 0;
398}
399
Dirk Behme53736ba2010-12-11 11:01:00 -0500400int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
401 const void *dout, void *din, unsigned long flags)
402{
403 struct omap3_spi_slave *ds = to_omap3_spi(slave);
404 unsigned int len;
Dirk Behme53736ba2010-12-11 11:01:00 -0500405 int ret = -1;
406
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300407 if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) {
408 printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen);
409 return -1;
410 }
411
412 if (bitlen % ds->slave.wordlen)
Dirk Behme53736ba2010-12-11 11:01:00 -0500413 return -1;
414
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300415 len = bitlen / ds->slave.wordlen;
Dirk Behme53736ba2010-12-11 11:01:00 -0500416
417 if (bitlen == 0) { /* only change CS */
418 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
419
420 if (flags & SPI_XFER_BEGIN) {
ajoycc1182b2012-11-17 21:10:15 +0000421 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
Dirk Behme53736ba2010-12-11 11:01:00 -0500422 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000423 omap3_spi_write_chconf(ds,chconf);
Dirk Behme53736ba2010-12-11 11:01:00 -0500424 }
425 if (flags & SPI_XFER_END) {
426 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
ajoycc1182b2012-11-17 21:10:15 +0000427 omap3_spi_write_chconf(ds,chconf);
428 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
Dirk Behme53736ba2010-12-11 11:01:00 -0500429 }
430 ret = 0;
431 } else {
jacopo mondi08b5ab02011-03-02 05:13:22 +0000432 if (dout != NULL && din != NULL)
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300433 ret = omap3_spi_txrx(slave, len, dout, din, flags);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000434 else if (dout != NULL)
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300435 ret = omap3_spi_write(slave, len, dout, flags);
jacopo mondi08b5ab02011-03-02 05:13:22 +0000436 else if (din != NULL)
Nikita Kiryanov5753d092013-10-16 17:23:25 +0300437 ret = omap3_spi_read(slave, len, din, flags);
Dirk Behme53736ba2010-12-11 11:01:00 -0500438 }
439 return ret;
440}
441
442int spi_cs_is_valid(unsigned int bus, unsigned int cs)
443{
444 return 1;
445}
446
447void spi_cs_activate(struct spi_slave *slave)
448{
449}
450
451void spi_cs_deactivate(struct spi_slave *slave)
452{
453}