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Aubrey Li65458982007-03-20 18:16:24 +08001/*
2 * U-boot - u-boot.lds.S
3 *
Mike Frysinger9171fc82008-03-30 15:46:13 -04004 * Copyright (c) 2005-2008 Analog Device Inc.
Aubrey Li65458982007-03-20 18:16:24 +08005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -040029#include <asm/blackfin.h>
30#undef ALIGN
Mike Frysingerb9eecc32008-10-24 17:48:54 -040031#undef ENTRY
32#undef bfin
Mike Frysinger9171fc82008-03-30 15:46:13 -040033
34/* If we don't actually load anything into L1 data, this will avoid
35 * a syntax error. If we do actually load something into L1 data,
36 * we'll get a linker memory load error (which is what we'd want).
37 * This is here in the first place so we can quickly test building
38 * for different CPU's which may lack non-cache L1 data.
39 */
40#ifndef L1_DATA_B_SRAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
Mike Frysinger9171fc82008-03-30 15:46:13 -040042# define L1_DATA_B_SRAM_SIZE 0
43#endif
Aubrey Li65458982007-03-20 18:16:24 +080044
Mike Frysinger02778f22009-04-24 23:39:41 -040045/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
46#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
47# define L1_CODE_ORIGIN L1_INST_SRAM
48#else
49# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
50#endif
51
Aubrey Li65458982007-03-20 18:16:24 +080052OUTPUT_ARCH(bfin)
Mike Frysinger9171fc82008-03-30 15:46:13 -040053
Mike Frysinger9171fc82008-03-30 15:46:13 -040054MEMORY
55{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
Mike Frysinger02778f22009-04-24 23:39:41 -040057 l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
Mike Frysinger7e1d2122008-10-18 04:04:49 -040058 l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
Mike Frysinger9171fc82008-03-30 15:46:13 -040059}
60
Mike Frysingerb9eecc32008-10-24 17:48:54 -040061ENTRY(_start)
Aubrey Li65458982007-03-20 18:16:24 +080062SECTIONS
63{
Mike Frysinger9171fc82008-03-30 15:46:13 -040064 .text :
65 {
Mike Frysingerb9eecc32008-10-24 17:48:54 -040066 cpu/blackfin/start.o (.text .text.*)
Mike Frysingerc23bff62008-10-11 20:47:58 -040067
Mike Frysinger9171fc82008-03-30 15:46:13 -040068#ifdef ENV_IS_EMBEDDED
69 /* WARNING - the following is hand-optimized to fit within
70 * the sector before the environment sector. If it throws
71 * an error during compilation remove an object here to get
72 * it linked after the configuration sector.
73 */
Aubrey Li65458982007-03-20 18:16:24 +080074
Mike Frysingerb9eecc32008-10-24 17:48:54 -040075 cpu/blackfin/traps.o (.text .text.*)
76 cpu/blackfin/interrupt.o (.text .text.*)
77 cpu/blackfin/serial.o (.text .text.*)
78 common/dlmalloc.o (.text .text.*)
79 lib_generic/crc32.o (.text .text.*)
80 lib_generic/zlib.o (.text .text.*)
81 board/bf561-ezkit/bf561-ezkit.o (.text .text.*)
Aubrey Li65458982007-03-20 18:16:24 +080082
Mike Frysinger9171fc82008-03-30 15:46:13 -040083 . = DEFINED(env_offset) ? env_offset : .;
Mike Frysingerb9eecc32008-10-24 17:48:54 -040084 common/env_embedded.o (.text .text.*)
Mike Frysinger9171fc82008-03-30 15:46:13 -040085#endif
Aubrey Li65458982007-03-20 18:16:24 +080086
Mike Frysingerc23bff62008-10-11 20:47:58 -040087 __initcode_start = .;
Mike Frysingerb9eecc32008-10-24 17:48:54 -040088 cpu/blackfin/initcode.o (.text .text.*)
Mike Frysingerc23bff62008-10-11 20:47:58 -040089 __initcode_end = .;
90
Mike Frysinger9171fc82008-03-30 15:46:13 -040091 *(.text .text.*)
92 } >ram
Aubrey Li65458982007-03-20 18:16:24 +080093
Mike Frysinger9171fc82008-03-30 15:46:13 -040094 .rodata :
95 {
96 . = ALIGN(4);
97 *(.rodata .rodata.*)
98 *(.rodata1)
99 *(.eh_frame)
100 . = ALIGN(4);
101 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800102
Mike Frysinger9171fc82008-03-30 15:46:13 -0400103 .data :
104 {
105 . = ALIGN(256);
106 *(.data .data.*)
107 *(.data1)
108 *(.sdata)
109 *(.sdata2)
110 *(.dynamic)
111 CONSTRUCTORS
112 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800113
Mike Frysinger9171fc82008-03-30 15:46:13 -0400114 .u_boot_cmd :
115 {
116 ___u_boot_cmd_start = .;
117 *(.u_boot_cmd)
118 ___u_boot_cmd_end = .;
119 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800120
Mike Frysinger9171fc82008-03-30 15:46:13 -0400121 .text_l1 :
122 {
123 . = ALIGN(4);
124 __stext_l1 = .;
125 *(.l1.text)
126 . = ALIGN(4);
127 __etext_l1 = .;
128 } >l1_code AT>ram
129 __stext_l1_lma = LOADADDR(.text_l1);
Aubrey Li65458982007-03-20 18:16:24 +0800130
Mike Frysinger9171fc82008-03-30 15:46:13 -0400131 .data_l1 :
132 {
133 . = ALIGN(4);
134 __sdata_l1 = .;
135 *(.l1.data)
136 *(.l1.bss)
137 . = ALIGN(4);
138 __edata_l1 = .;
139 } >l1_data AT>ram
140 __sdata_l1_lma = LOADADDR(.data_l1);
Aubrey Li65458982007-03-20 18:16:24 +0800141
Mike Frysinger9171fc82008-03-30 15:46:13 -0400142 .bss :
143 {
144 . = ALIGN(4);
145 __bss_start = .;
146 *(.sbss) *(.scommon)
147 *(.dynbss)
148 *(.bss .bss.*)
149 *(COMMON)
150 __bss_end = .;
151 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800152}