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Wolfgang Denk8cba0902006-05-12 16:15:46 +02001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2006-2008
Wolfgang Denk8cba0902006-05-12 16:15:46 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
38#define CONFIG_TQM8xxL 1
39
Wolfgang Denk8cba0902006-05-12 16:15:46 +020040#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41#undef CONFIG_8xx_CONS_SMC2
42#undef CONFIG_8xx_CONS_NONE
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
45#define CONFIG_BOOTCOUNT_LIMIT
46
47#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010051#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
Wolfgang Denk8cba0902006-05-12 16:15:46 +020052
53#undef CONFIG_BOOTARGS
54
55#define CONFIG_EXTRA_ENV_SETTINGS \
56 "netdev=eth0\0" \
57 "nfsargs=setenv bootargs root=/dev/nfs rw " \
58 "nfsroot=${serverip}:${rootpath}\0" \
59 "ramargs=setenv bootargs root=/dev/ram rw\0" \
60 "addip=setenv bootargs ${bootargs} " \
61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
62 ":${hostname}:${netdev}:off panic=1\0" \
63 "flash_nfs=run nfsargs addip;" \
64 "bootm ${kernel_addr}\0" \
65 "flash_self=run ramargs addip;" \
66 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
67 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
68 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020069 "hostname=virtlab2\0" \
70 "bootfile=virtlab2/uImage\0" \
71 "fdt_addr=40040000\0" \
72 "kernel_addr=40060000\0" \
73 "ramdisk_addr=40200000\0" \
74 "u-boot=virtlab2/u-image.bin\0" \
75 "load=tftp 200000 ${u-boot}\0" \
76 "update=prot off 40000000 +${filesize};" \
77 "era 40000000 +${filesize};" \
78 "cp.b 200000 40000000 ${filesize};" \
79 "sete filesize;save\0" \
Wolfgang Denk8cba0902006-05-12 16:15:46 +020080 ""
81#define CONFIG_BOOTCOMMAND "run flash_self"
82
83#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Wolfgang Denk8cba0902006-05-12 16:15:46 +020085
86#undef CONFIG_WATCHDOG /* watchdog disabled */
87
88#if defined(CONFIG_LCD)
89# undef CONFIG_STATUS_LED /* disturbs display */
90#else
91# define CONFIG_STATUS_LED 1 /* Status LED enabled */
92#endif /* CONFIG_LCD */
93
94#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
95
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050096/*
97 * BOOTP options
98 */
99#define CONFIG_BOOTP_SUBNETMASK
100#define CONFIG_BOOTP_GATEWAY
101#define CONFIG_BOOTP_HOSTNAME
102#define CONFIG_BOOTP_BOOTPATH
103#define CONFIG_BOOTP_BOOTFILESIZE
104
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200105
106#define CONFIG_MAC_PARTITION
107#define CONFIG_DOS_PARTITION
108
109#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
110
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500111
112/*
113 * Command line configuration.
114 */
115#include <config_cmd_default.h>
116
117#define CONFIG_CMD_ASKENV
118#define CONFIG_CMD_DATE
119#define CONFIG_CMD_DHCP
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100120#define CONFIG_CMD_EXT2
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500121#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200122#define CONFIG_CMD_JFFS2
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500123#define CONFIG_CMD_NFS
124#define CONFIG_CMD_SNTP
125
126#if defined(CONFIG_SPLASH_SCREEN)
127 #define CONFIG_CMD_BMP
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200128#endif
129
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200130
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200131#define CONFIG_NETCONSOLE
132
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200133/*
134 * Miscellaneous configurable options
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200138
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200139#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
141#ifdef CONFIG_SYS_HUSH_PARSER
142#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200143#endif
144
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500145#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200147#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200149#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
155#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200162
163/*
164 * Low Level Configuration Settings
165 * (address mappings, register initial values, etc.)
166 * You should know what you are doing if you make changes here.
167 */
168/*-----------------------------------------------------------------------
169 * Internal Memory Mapped Register
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_IMMR 0xFFF00000
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200172
173/*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area (in DPRAM)
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
177#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
178#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
179#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
180#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200181
182/*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration
184 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_SDRAM_BASE 0x00000000
188#define CONFIG_SYS_FLASH_BASE 0x40000000
189#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
190#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
191#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200192
193/*
194 * For booting Linux, the board info and command line data
195 * have to be in the first 8 MB of memory, since this is
196 * the maximum mapped by the Linux kernel during initialization.
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200199
200/*-----------------------------------------------------------------------
201 * FLASH organization
202 */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200203
Martin Krausee318d9e2007-09-27 11:10:08 +0200204/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200206#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
208#define CONFIG_SYS_FLASH_EMPTY_INFO
209#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
210#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
211#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200212
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200213#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200214#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
215#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200216
217/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
219#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200222
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200223#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
224
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200225/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200226 * Dynamic MTD partition support
227 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100228#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200229#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
230#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200231#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
232
233#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
234 "128k(dtb)," \
235 "1664k(kernel)," \
236 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200237 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200238
239/*-----------------------------------------------------------------------
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200240 * Hardware Information Block
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
243#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
244#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200245
246/*-----------------------------------------------------------------------
247 * Cache Configuration
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500250#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200252#endif
253
254/*-----------------------------------------------------------------------
255 * SYPCR - System Protection Control 11-9
256 * SYPCR can only be written once after reset!
257 *-----------------------------------------------------------------------
258 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
259 */
260#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200262 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
263#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200265#endif
266
267/*-----------------------------------------------------------------------
268 * SIUMCR - SIU Module Configuration 11-6
269 *-----------------------------------------------------------------------
270 * PCMCIA config., multi-function pin tri-state
271 */
272#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200274#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200276#endif /* CONFIG_CAN_DRIVER */
277
278/*-----------------------------------------------------------------------
279 * TBSCR - Time Base Status and Control 11-26
280 *-----------------------------------------------------------------------
281 * Clear Reference Interrupt Status, Timebase freezing enabled
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200284
285/*-----------------------------------------------------------------------
286 * RTCSC - Real-Time Clock Status and Control Register 11-27
287 *-----------------------------------------------------------------------
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200290
291/*-----------------------------------------------------------------------
292 * PISCR - Periodic Interrupt Status and Control 11-31
293 *-----------------------------------------------------------------------
294 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
295 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200297
298/*-----------------------------------------------------------------------
299 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
300 *-----------------------------------------------------------------------
301 * Reset PLL lock status sticky bit, timer expired status bit and timer
302 * interrupt status bit
303 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200305
306/*-----------------------------------------------------------------------
307 * SCCR - System Clock and reset Control Register 15-27
308 *-----------------------------------------------------------------------
309 * Set clock output, timebase and RTC source and divider,
310 * power management and some other internal clocks
311 */
312#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200314 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
315 SCCR_DFALCD00)
316
317/*-----------------------------------------------------------------------
318 * PCMCIA stuff
319 *-----------------------------------------------------------------------
320 *
321 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
323#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
324#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
325#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
326#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
327#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
328#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
329#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200330
331/*-----------------------------------------------------------------------
332 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
333 *-----------------------------------------------------------------------
334 */
335
336#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
337
338#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
339#undef CONFIG_IDE_LED /* LED for ide not supported */
340#undef CONFIG_IDE_RESET /* reset for ide not supported */
341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
343#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200348
349/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200351
352/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200354
355/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200357
358/*-----------------------------------------------------------------------
359 *
360 *-----------------------------------------------------------------------
361 *
362 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_DER 0
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200364
365/*
366 * Init Memory Controller:
367 *
368 * BR0/1 and OR0/1 (FLASH)
369 */
370
371#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
372#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
373
374/* used to re-map FLASH both when starting from SRAM or FLASH:
375 * restrict access enough to keep SRAM working (if any)
376 * but not too much to meddle with FLASH accesses
377 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
379#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200380
381/*
382 * FLASH timing:
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200385 OR_SCY_3_CLK | OR_EHTR | OR_BI)
386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
388#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
389#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
392#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
393#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200394
395/*
396 * BR2/3 and OR2/3 (SDRAM)
397 *
398 */
399#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
400#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
401#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
402
403/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200405
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
407#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200408
409#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
411#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200412#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
414#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
415#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
416#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200417 BR_PS_8 | BR_MS_UPMB | BR_V )
418#endif /* CONFIG_CAN_DRIVER */
419
420/*
421 * Memory Periodic Timer Prescaler
422 *
423 * The Divider for PTA (refresh timer) configuration is based on an
424 * example SDRAM configuration (64 MBit, one bank). The adjustment to
425 * the number of chip selects (NCS) and the actually needed refresh
426 * rate is done by setting MPTPR.
427 *
428 * PTA is calculated from
429 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
430 *
431 * gclk CPU clock (not bus clock!)
432 * Trefresh Refresh cycle * 4 (four word bursts used)
433 *
434 * 4096 Rows from SDRAM example configuration
435 * 1000 factor s -> ms
436 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
437 * 4 Number of refresh cycles per period
438 * 64 Refresh cycle in ms per number of rows
439 * --------------------------------------------
440 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
441 *
442 * 50 MHz => 50.000.000 / Divider = 98
443 * 66 Mhz => 66.000.000 / Divider = 129
444 * 80 Mhz => 80.000.000 / Divider = 156
445 */
446
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
448#define CONFIG_SYS_MAMR_PTA 98
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200449
450/*
451 * For 16 MBit, refresh rates could be 31.3 us
452 * (= 64 ms / 2K = 125 / quad bursts).
453 * For a simpler initialization, 15.6 us is used instead.
454 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
456 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200457 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
459#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200460
461/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
463#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200464
465/*
466 * MAMR settings for SDRAM
467 */
468
469/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200471 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
472 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
473/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200475 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
476 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
477
478
479/*
480 * Internal Definitions
481 *
482 * Boot Flags
483 */
484#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
485#define BOOTFLAG_WARM 0x02 /* Software reboot */
486
487/* Map peripheral control registers on CS4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000
489#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
490#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200491 OR_SCY_2_CLK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
493#define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200494#endif /* __CONFIG_H */