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Wolfgang Denk72a087e2006-10-24 14:27:35 +02001/*
2 * Register definitions for System Manager
3 */
4#ifndef __CPU_AT32AP_SM_H__
5#define __CPU_AT32AP_SM_H__
6
7/* SM register offsets */
8#define SM_PM_MCCTRL 0x0000
9#define SM_PM_CKSEL 0x0004
10#define SM_PM_CPU_MASK 0x0008
11#define SM_PM_HSB_MASK 0x000c
12#define SM_PM_PBA_MASK 0x0010
13#define SM_PM_PBB_MASK 0x0014
14#define SM_PM_PLL0 0x0020
15#define SM_PM_PLL1 0x0024
16#define SM_PM_VCTRL 0x0030
17#define SM_PM_VMREF 0x0034
18#define SM_PM_VMV 0x0038
19#define SM_PM_IER 0x0040
20#define SM_PM_IDR 0x0044
21#define SM_PM_IMR 0x0048
22#define SM_PM_ISR 0x004c
23#define SM_PM_ICR 0x0050
24#define SM_PM_GCCTRL 0x0060
25#define SM_RTC_CTRL 0x0080
26#define SM_RTC_VAL 0x0084
27#define SM_RTC_TOP 0x0088
28#define SM_RTC_IER 0x0090
29#define SM_RTC_IDR 0x0094
30#define SM_RTC_IMR 0x0098
31#define SM_RTC_ISR 0x009c
32#define SM_RTC_ICR 0x00a0
33#define SM_WDT_CTRL 0x00b0
34#define SM_WDT_CLR 0x00b4
35#define SM_WDT_EXT 0x00b8
36#define SM_RC_RCAUSE 0x00c0
37#define SM_EIM_IER 0x0100
38#define SM_EIM_IDR 0x0104
39#define SM_EIM_IMR 0x0108
40#define SM_EIM_ISR 0x010c
41#define SM_EIM_ICR 0x0110
42#define SM_EIM_MODE 0x0114
43#define SM_EIM_EDGE 0x0118
44#define SM_EIM_LEVEL 0x011c
45#define SM_EIM_TEST 0x0120
46#define SM_EIM_NMIC 0x0124
47
48/* Bitfields in PM_CKSEL */
49#define SM_CPUSEL_OFFSET 0
50#define SM_CPUSEL_SIZE 3
51#define SM_CPUDIV_OFFSET 7
52#define SM_CPUDIV_SIZE 1
53#define SM_HSBSEL_OFFSET 8
54#define SM_HSBSEL_SIZE 3
55#define SM_HSBDIV_OFFSET 15
56#define SM_HSBDIV_SIZE 1
57#define SM_PBASEL_OFFSET 16
58#define SM_PBASEL_SIZE 3
59#define SM_PBADIV_OFFSET 23
60#define SM_PBADIV_SIZE 1
61#define SM_PBBSEL_OFFSET 24
62#define SM_PBBSEL_SIZE 3
63#define SM_PBBDIV_OFFSET 31
64#define SM_PBBDIV_SIZE 1
65
66/* Bitfields in PM_PLL0 */
67#define SM_PLLEN_OFFSET 0
68#define SM_PLLEN_SIZE 1
69#define SM_PLLOSC_OFFSET 1
70#define SM_PLLOSC_SIZE 1
71#define SM_PLLOPT_OFFSET 2
72#define SM_PLLOPT_SIZE 3
73#define SM_PLLDIV_OFFSET 8
74#define SM_PLLDIV_SIZE 8
75#define SM_PLLMUL_OFFSET 16
76#define SM_PLLMUL_SIZE 8
77#define SM_PLLCOUNT_OFFSET 24
78#define SM_PLLCOUNT_SIZE 6
79#define SM_PLLTEST_OFFSET 31
80#define SM_PLLTEST_SIZE 1
81
82/* Bitfields in PM_VCTRL */
83#define SM_VAUTO_OFFSET 0
84#define SM_VAUTO_SIZE 1
85#define SM_PM_VCTRL_VAL_OFFSET 8
86#define SM_PM_VCTRL_VAL_SIZE 7
87
88/* Bitfields in PM_VMREF */
89#define SM_REFSEL_OFFSET 0
90#define SM_REFSEL_SIZE 4
91
92/* Bitfields in PM_VMV */
93#define SM_PM_VMV_VAL_OFFSET 0
94#define SM_PM_VMV_VAL_SIZE 8
95
96/* Bitfields in PM_ICR */
97#define SM_LOCK0_OFFSET 0
98#define SM_LOCK0_SIZE 1
99#define SM_LOCK1_OFFSET 1
100#define SM_LOCK1_SIZE 1
101#define SM_WAKE_OFFSET 2
102#define SM_WAKE_SIZE 1
103#define SM_VOK_OFFSET 3
104#define SM_VOK_SIZE 1
105#define SM_VMRDY_OFFSET 4
106#define SM_VMRDY_SIZE 1
107#define SM_CKRDY_OFFSET 5
108#define SM_CKRDY_SIZE 1
109
110/* Bitfields in PM_GCCTRL */
111#define SM_OSCSEL_OFFSET 0
112#define SM_OSCSEL_SIZE 1
113#define SM_PLLSEL_OFFSET 1
114#define SM_PLLSEL_SIZE 1
115#define SM_CEN_OFFSET 2
116#define SM_CEN_SIZE 1
117#define SM_CPC_OFFSET 3
118#define SM_CPC_SIZE 1
119#define SM_DIVEN_OFFSET 4
120#define SM_DIVEN_SIZE 1
121#define SM_DIV_OFFSET 8
122#define SM_DIV_SIZE 8
123
124/* Bitfields in RTC_CTRL */
125#define SM_PCLR_OFFSET 1
126#define SM_PCLR_SIZE 1
127#define SM_TOPEN_OFFSET 2
128#define SM_TOPEN_SIZE 1
129#define SM_CLKEN_OFFSET 3
130#define SM_CLKEN_SIZE 1
131#define SM_PSEL_OFFSET 8
132#define SM_PSEL_SIZE 16
133
134/* Bitfields in RTC_VAL */
135#define SM_RTC_VAL_VAL_OFFSET 0
136#define SM_RTC_VAL_VAL_SIZE 31
137
138/* Bitfields in RTC_TOP */
139#define SM_RTC_TOP_VAL_OFFSET 0
140#define SM_RTC_TOP_VAL_SIZE 32
141
142/* Bitfields in RTC_ICR */
143#define SM_TOPI_OFFSET 0
144#define SM_TOPI_SIZE 1
145
146/* Bitfields in WDT_CTRL */
147#define SM_KEY_OFFSET 24
148#define SM_KEY_SIZE 8
149
150/* Bitfields in RC_RCAUSE */
151#define SM_POR_OFFSET 0
152#define SM_POR_SIZE 1
153#define SM_BOD_OFFSET 1
154#define SM_BOD_SIZE 1
155#define SM_EXT_OFFSET 2
156#define SM_EXT_SIZE 1
157#define SM_WDT_OFFSET 3
158#define SM_WDT_SIZE 1
159#define SM_NTAE_OFFSET 4
160#define SM_NTAE_SIZE 1
161#define SM_SERP_OFFSET 5
162#define SM_SERP_SIZE 1
163
164/* Bitfields in EIM_EDGE */
165#define SM_INT0_OFFSET 0
166#define SM_INT0_SIZE 1
167#define SM_INT1_OFFSET 1
168#define SM_INT1_SIZE 1
169#define SM_INT2_OFFSET 2
170#define SM_INT2_SIZE 1
171#define SM_INT3_OFFSET 3
172#define SM_INT3_SIZE 1
173
174/* Bitfields in EIM_LEVEL */
175
176/* Bitfields in EIM_TEST */
177#define SM_TESTEN_OFFSET 31
178#define SM_TESTEN_SIZE 1
179
180/* Bitfields in EIM_NMIC */
181#define SM_EN_OFFSET 0
182#define SM_EN_SIZE 1
183
184/* Bit manipulation macros */
185#define SM_BIT(name) \
186 (1 << SM_##name##_OFFSET)
187#define SM_BF(name,value) \
188 (((value) & ((1 << SM_##name##_SIZE) - 1)) \
189 << SM_##name##_OFFSET)
190#define SM_BFEXT(name,value) \
191 (((value) >> SM_##name##_OFFSET) \
192 & ((1 << SM_##name##_SIZE) - 1))
193#define SM_BFINS(name,value,old) \
194 (((old) & ~(((1 << SM_##name##_SIZE) - 1) \
195 << SM_##name##_OFFSET)) \
196 | SM_BF(name,value))
197
198/* Register access macros */
Haavard Skinnemoendf548d32006-11-19 18:06:53 +0100199#define sm_readl(reg) \
200 readl((void *)SM_BASE + SM_##reg)
201#define sm_writel(reg,value) \
202 writel((value), (void *)SM_BASE + SM_##reg)
Wolfgang Denk72a087e2006-10-24 14:27:35 +0200203
204#endif /* __CPU_AT32AP_SM_H__ */