blob: 2c40e711a1db3208d40004a0f50604d5f0cb9b08 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glasscb3b2e62015-01-01 16:18:15 -07002/*
3 * (C) Copyright 2014 Google, Inc
Simon Glasscb3b2e62015-01-01 16:18:15 -07004 */
5
6#include <common.h>
Simon Glass09140112020-05-10 11:40:03 -06007#include <command.h>
Simon Glasscb3b2e62015-01-01 16:18:15 -07008#include <asm/msr.h>
9#include <asm/mtrr.h>
10
11static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
12 "Uncacheable",
13 "Combine",
14 "2",
15 "3",
16 "Through",
17 "Protect",
18 "Back",
19};
20
21static int do_mtrr_list(void)
22{
23 int i;
24
25 printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
26 "Mask ||", "Size ||");
27 for (i = 0; i < MTRR_COUNT; i++) {
28 const char *type = "Invalid";
29 uint64_t base, mask, size;
30 bool valid;
31
32 base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
33 mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
34 size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
35 size |= (1 << 12) - 1;
36 size += 1;
37 valid = mask & MTRR_PHYS_MASK_VALID;
38 type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
39 printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
Bin Mengdf07d912015-07-06 16:31:32 +080040 valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
41 mask & ~MTRR_PHYS_MASK_VALID, size);
Simon Glasscb3b2e62015-01-01 16:18:15 -070042 }
43
44 return 0;
45}
46
Simon Glass09140112020-05-10 11:40:03 -060047static int do_mtrr_set(uint reg, int argc, char *const argv[])
Simon Glasscb3b2e62015-01-01 16:18:15 -070048{
49 const char *typename = argv[0];
50 struct mtrr_state state;
51 uint32_t start, size;
52 uint64_t base, mask;
53 int i, type = -1;
54 bool valid;
55
56 if (argc < 3)
57 return CMD_RET_USAGE;
58 for (i = 0; i < MTRR_TYPE_COUNT; i++) {
59 if (*typename == *mtrr_type_name[i])
60 type = i;
61 }
62 if (type == -1) {
63 printf("Invalid type name %s\n", typename);
64 return CMD_RET_USAGE;
65 }
66 start = simple_strtoul(argv[1], NULL, 16);
67 size = simple_strtoul(argv[2], NULL, 16);
68
69 base = start | type;
70 valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
71 mask = ~((uint64_t)size - 1);
72 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
73 if (valid)
74 mask |= MTRR_PHYS_MASK_VALID;
75
76 printf("base=%llx, mask=%llx\n", base, mask);
Simon Glass590cee82018-10-01 12:22:37 -060077 mtrr_open(&state, true);
Simon Glasscb3b2e62015-01-01 16:18:15 -070078 wrmsrl(MTRR_PHYS_BASE_MSR(reg), base);
79 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
Simon Glass590cee82018-10-01 12:22:37 -060080 mtrr_close(&state, true);
Simon Glasscb3b2e62015-01-01 16:18:15 -070081
82 return 0;
83}
84
85static int mtrr_set_valid(int reg, bool valid)
86{
87 struct mtrr_state state;
88 uint64_t mask;
89
Simon Glass590cee82018-10-01 12:22:37 -060090 mtrr_open(&state, true);
Simon Glasscb3b2e62015-01-01 16:18:15 -070091 mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg));
92 if (valid)
93 mask |= MTRR_PHYS_MASK_VALID;
94 else
95 mask &= ~MTRR_PHYS_MASK_VALID;
96 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
Simon Glass590cee82018-10-01 12:22:37 -060097 mtrr_close(&state, true);
Simon Glasscb3b2e62015-01-01 16:18:15 -070098
99 return 0;
100}
101
Simon Glass09140112020-05-10 11:40:03 -0600102static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc,
103 char *const argv[])
Simon Glasscb3b2e62015-01-01 16:18:15 -0700104{
105 const char *cmd;
106 uint reg;
107
108 cmd = argv[1];
109 if (argc < 2 || *cmd == 'l')
110 return do_mtrr_list();
111 argc -= 2;
112 argv += 2;
113 if (argc <= 0)
114 return CMD_RET_USAGE;
115 reg = simple_strtoul(argv[0], NULL, 16);
116 if (reg >= MTRR_COUNT) {
117 printf("Invalid register number\n");
118 return CMD_RET_USAGE;
119 }
120 if (*cmd == 'e')
121 return mtrr_set_valid(reg, true);
122 else if (*cmd == 'd')
123 return mtrr_set_valid(reg, false);
124 else if (*cmd == 's')
125 return do_mtrr_set(reg, argc - 1, argv + 1);
126 else
127 return CMD_RET_USAGE;
128
129 return 0;
130}
131
132U_BOOT_CMD(
133 mtrr, 6, 1, do_mtrr,
134 "Use x86 memory type range registers (32-bit only)",
135 "[list] - list current registers\n"
136 "set <reg> <type> <start> <size> - set a register\n"
137 "\t<type> is Uncacheable, Combine, Through, Protect, Back\n"
138 "disable <reg> - disable a register\n"
139 "ensable <reg> - enable a register"
140);