Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a45fa436854a4116c19dd8794c9b033a3cf117bc / . / arch / arm / cpu / tegra20-common / pinmux.c
blob: 9e34c8bec07555dfb091877d5834263b615b8516 [file] [log] [blame]
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]5 */
6
Allen Martin00a27492012-08-31 08:30:00 +0000[diff] [blame]7/* Tegra20 pin multiplexing functions */
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]8
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]9#include <common.h>
Tom Warren150c2492012-09-19 15:50:56 -0700[diff] [blame]10#include <asm/io.h>
Tom Warren150c2492012-09-19 15:50:56 -0700[diff] [blame]11#include <asm/arch/pinmux.h>
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]12
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]13/*
14 * This defines the order of the pin mux control bits in the registers. For
15 * some reason there is no correspendence between the tristate, pin mux and
16 * pullup/pulldown registers.
17 */
18enum pmux_ctlid {
19 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
20 MUXCTL_UAA,
21 MUXCTL_UAB,
22 MUXCTL_UAC,
23 MUXCTL_UAD,
24 MUXCTL_UDA,
25 MUXCTL_RESERVED5,
26 MUXCTL_ATE,
27 MUXCTL_RM,
28
29 MUXCTL_ATB,
30 MUXCTL_RESERVED9,
31 MUXCTL_ATD,
32 MUXCTL_ATC,
33 MUXCTL_ATA,
34 MUXCTL_KBCF,
35 MUXCTL_KBCE,
36 MUXCTL_SDMMC1,
37
38 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
39 MUXCTL_GMA,
40 MUXCTL_GMC,
41 MUXCTL_HDINT,
42 MUXCTL_SLXA,
43 MUXCTL_OWC,
44 MUXCTL_SLXC,
45 MUXCTL_SLXD,
46 MUXCTL_SLXK,
47
48 MUXCTL_UCA,
49 MUXCTL_UCB,
50 MUXCTL_DTA,
51 MUXCTL_DTB,
52 MUXCTL_RESERVED28,
53 MUXCTL_DTC,
54 MUXCTL_DTD,
55 MUXCTL_DTE,
56
57 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
58 MUXCTL_DDC,
59 MUXCTL_CDEV1,
60 MUXCTL_CDEV2,
61 MUXCTL_CSUS,
62 MUXCTL_I2CP,
63 MUXCTL_KBCA,
64 MUXCTL_KBCB,
65 MUXCTL_KBCC,
66
67 MUXCTL_IRTX,
68 MUXCTL_IRRX,
69 MUXCTL_DAP1,
70 MUXCTL_DAP2,
71 MUXCTL_DAP3,
72 MUXCTL_DAP4,
73 MUXCTL_GMB,
74 MUXCTL_GMD,
75
76 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
77 MUXCTL_GME,
78 MUXCTL_GPV,
79 MUXCTL_GPU,
80 MUXCTL_SPDO,
81 MUXCTL_SPDI,
82 MUXCTL_SDB,
83 MUXCTL_SDC,
84 MUXCTL_SDD,
85
86 MUXCTL_SPIH,
87 MUXCTL_SPIG,
88 MUXCTL_SPIF,
89 MUXCTL_SPIE,
90 MUXCTL_SPID,
91 MUXCTL_SPIC,
92 MUXCTL_SPIB,
93 MUXCTL_SPIA,
94
95 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
96 MUXCTL_LPW0,
97 MUXCTL_LPW1,
98 MUXCTL_LPW2,
99 MUXCTL_LSDI,
100 MUXCTL_LSDA,
101 MUXCTL_LSPI,
102 MUXCTL_LCSN,
103 MUXCTL_LDC,
104
105 MUXCTL_LSCK,
106 MUXCTL_LSC0,
107 MUXCTL_LSC1,
108 MUXCTL_LHS,
109 MUXCTL_LVS,
110 MUXCTL_LM0,
111 MUXCTL_LM1,
112 MUXCTL_LVP0,
113
114 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
115 MUXCTL_LD0,
116 MUXCTL_LD1,
117 MUXCTL_LD2,
118 MUXCTL_LD3,
119 MUXCTL_LD4,
120 MUXCTL_LD5,
121 MUXCTL_LD6,
122 MUXCTL_LD7,
123
124 MUXCTL_LD8,
125 MUXCTL_LD9,
126 MUXCTL_LD10,
127 MUXCTL_LD11,
128 MUXCTL_LD12,
129 MUXCTL_LD13,
130 MUXCTL_LD14,
131 MUXCTL_LD15,
132
133 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
134 MUXCTL_LD16,
135 MUXCTL_LD17,
136 MUXCTL_LHP1,
137 MUXCTL_LHP2,
138 MUXCTL_LVP1,
139 MUXCTL_LHP0,
140 MUXCTL_RESERVED102,
141 MUXCTL_LPP,
142
143 MUXCTL_LDI,
144 MUXCTL_PMC,
145 MUXCTL_CRTP,
146 MUXCTL_PTA,
147 MUXCTL_RESERVED108,
148 MUXCTL_KBCD,
149 MUXCTL_GPU7,
150 MUXCTL_DTF,
151
152 MUXCTL_NONE = -1,
153};
154
155/*
156 * And this defines the order of the pullup/pulldown controls which are again
157 * in a different order
158 */
159enum pmux_pullid {
160 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
161 PUCTL_ATA,
162 PUCTL_ATB,
163 PUCTL_ATC,
164 PUCTL_ATD,
165 PUCTL_ATE,
166 PUCTL_DAP1,
167 PUCTL_DAP2,
168 PUCTL_DAP3,
169
170 PUCTL_DAP4,
171 PUCTL_DTA,
172 PUCTL_DTB,
173 PUCTL_DTC,
174 PUCTL_DTD,
175 PUCTL_DTE,
176 PUCTL_DTF,
177 PUCTL_GPV,
178
179 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
180 PUCTL_RM,
181 PUCTL_I2CP,
182 PUCTL_PTA,
183 PUCTL_GPU7,
184 PUCTL_KBCA,
185 PUCTL_KBCB,
186 PUCTL_KBCC,
187 PUCTL_KBCD,
188
189 PUCTL_SPDI,
190 PUCTL_SPDO,
191 PUCTL_GPSLXAU,
192 PUCTL_CRTP,
193 PUCTL_SLXC,
194 PUCTL_SLXD,
195 PUCTL_SLXK,
196
197 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
198 PUCTL_CDEV1,
199 PUCTL_CDEV2,
200 PUCTL_SPIA,
201 PUCTL_SPIB,
202 PUCTL_SPIC,
203 PUCTL_SPID,
204 PUCTL_SPIE,
205 PUCTL_SPIF,
206
207 PUCTL_SPIG,
208 PUCTL_SPIH,
209 PUCTL_IRTX,
210 PUCTL_IRRX,
211 PUCTL_GME,
212 PUCTL_RESERVED45,
213 PUCTL_XM2D,
214 PUCTL_XM2C,
215
216 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
217 PUCTL_UAA,
218 PUCTL_UAB,
219 PUCTL_UAC,
220 PUCTL_UAD,
221 PUCTL_UCA,
222 PUCTL_UCB,
223 PUCTL_LD17,
224 PUCTL_LD19_18,
225
226 PUCTL_LD21_20,
227 PUCTL_LD23_22,
228 PUCTL_LS,
229 PUCTL_LC,
230 PUCTL_CSUS,
231 PUCTL_DDRC,
232 PUCTL_SDC,
233 PUCTL_SDD,
234
235 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
236 PUCTL_KBCF,
237 PUCTL_KBCE,
238 PUCTL_PMCA,
239 PUCTL_PMCB,
240 PUCTL_PMCC,
241 PUCTL_PMCD,
242 PUCTL_PMCE,
243 PUCTL_CK32,
244
245 PUCTL_UDA,
246 PUCTL_SDMMC1,
247 PUCTL_GMA,
248 PUCTL_GMB,
249 PUCTL_GMC,
250 PUCTL_GMD,
251 PUCTL_DDC,
252 PUCTL_OWC,
253
254 PUCTL_NONE = -1
255};
256
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]257/* Convenient macro for defining pin group properties */
258#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
259 { \
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]260 .funcs = { \
261 PMUX_FUNC_ ## f0, \
262 PMUX_FUNC_ ## f1, \
263 PMUX_FUNC_ ## f2, \
264 PMUX_FUNC_ ## f3, \
265 }, \
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]266 .ctl_id = mux, \
267 .pull_id = pupd \
268 }
269
270/* A normal pin group where the mux name and pull-up name match */
271#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
272 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
273 MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
274
275/* A pin group where the pull-up name doesn't have a 1-1 mapping */
276#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
277 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
278 MUXCTL_ ## pg_name, PUCTL_ ## pupd)
279
280/* A pin group number which is not used */
281#define PIN_RESERVED \
Stephen Warren6ac1e542014-03-21 12:28:51 -0600[diff] [blame]282 PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
283
Stephen Warrene2969952014-03-21 12:28:54 -0600[diff] [blame]284#define PMUX_FUNC_RSVD PMUX_FUNC_RSVD1
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]285
Stephen Warrene2969952014-03-21 12:28:54 -0600[diff] [blame]286static const struct tegra_pingroup_desc tegra20_pingroups[] = {
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]287 PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
288 PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
289 PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
290 PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
291 PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
292 PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
293 PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
294 PLLC_OUT1),
295 PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
296
297 PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
298 PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
299 PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
300 PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
301 PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
302 PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
303 PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
304 PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
305
306 PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
307 GPSLXAU),
308 PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
309 PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
310 PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
311 PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
312 PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
313 PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
314 PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
315
316 PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
317 PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
318 PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
319 PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
320 PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
321 PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
322 PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
323 PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
324
325 PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
326 PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
327 PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
328 PIN_RESERVED,
329 PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
330 PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
331 PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
332 PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
333
334 PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
335 PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
336 PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
337 PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
338 PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
339 PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
340 PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
341 PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
342
343 PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
344 PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
345 PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
346 PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
347 PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
Allen Martind08b9e92013-01-09 10:52:23 +0000[diff] [blame]348 PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]349 PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
350 PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
351
352 PIN_RESERVED,
353 PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
354 PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
355 PIN_RESERVED,
356 PIN_RESERVED,
357 PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
358 PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
359 PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
360
361 /* 64 */
362 PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
363 PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
364 PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
365 PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
366 PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
367 PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
368 PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
369 PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
370
371 PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
372 PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
373 PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
374 PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
375 PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
376 PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
377 PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
378 PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
379
380 PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
381 PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
382 PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
383 PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
384 PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
385 PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
386 PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
387 PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
388
389 PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
390 PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
391 PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
392 PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
393 PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
394 PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
395 PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
396 PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
397
398 /* 96 */
399 PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
400 PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
401 PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
402 PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
403 PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
404 PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
405 PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
406 PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
407
408 PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
409 PIN_RESERVED,
410 PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
411 PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
412 PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
413 PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
414 PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
415 PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
416
417 /* these pin groups only have pullup and pull down control */
418 PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
419 PUCTL_NONE),
420 PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
421 PUCTL_NONE),
422 PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
423 PUCTL_NONE),
424 PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
425 PUCTL_NONE),
426 PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
427 PUCTL_NONE),
428 PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
429 PUCTL_NONE),
430 PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
431 PUCTL_NONE),
432 PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
433 PUCTL_NONE),
434 PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
435 PUCTL_NONE),
436};
Stephen Warrene2969952014-03-21 12:28:54 -0600[diff] [blame]437const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra20_pingroups;