blob: ad075b80b84b41e8790cb245c9836f05799570a5 [file] [log] [blame]
wdenkab255f22002-09-18 09:04:55 +00001/*
2 * (C) Copyright 2001
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405CR 1 /* This is a PPC405CR CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_CANBT 1 /* ...on a CANBT board */
wdenkab255f22002-09-18 09:04:55 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkab255f22002-09-18 09:04:55 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenkab255f22002-09-18 09:04:55 +000043
44#define CONFIG_BAUDRATE 115200
45#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
46
47#undef CONFIG_BOOTARGS
48#define CONFIG_BOOTCOMMAND \
49 "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
50 "bootm ffe00000 ffe80000"
51
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkab255f22002-09-18 09:04:55 +000054
wdenkc837dcb2004-01-20 23:12:12 +000055#undef CONFIG_PCI_PNP /* no pci plug-and-play */
wdenkab255f22002-09-18 09:04:55 +000056
wdenkc837dcb2004-01-20 23:12:12 +000057#define CONFIG_PHY_ADDR 0 /* PHY address */
wdenkab255f22002-09-18 09:04:55 +000058
wdenkab255f22002-09-18 09:04:55 +000059
Jon Loeliger49cf7e82007-07-05 19:52:35 -050060/*
Jon Loeliger11799432007-07-10 09:02:57 -050061 * BOOTP options
62 */
63#define CONFIG_BOOTP_BOOTFILESIZE
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_GATEWAY
66#define CONFIG_BOOTP_HOSTNAME
67
68
69/*
Jon Loeliger49cf7e82007-07-05 19:52:35 -050070 * Command line configuration.
71 */
72#include <config_cmd_default.h>
73
74#define CONFIG_CMD_IRQ
Wolfgang Denk5728be32007-08-06 01:01:49 +020075#define CONFIG_CMD_EEPROM
Jon Loeliger49cf7e82007-07-05 19:52:35 -050076
77#undef CONFIG_CMD_NET
78
wdenkab255f22002-09-18 09:04:55 +000079
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81
wdenkc837dcb2004-01-20 23:12:12 +000082#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkab255f22002-09-18 09:04:55 +000083
84/*
85 * Miscellaneous configurable options
86 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_LONGHELP /* undef to save memory */
88#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050089#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkab255f22002-09-18 09:04:55 +000091#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkab255f22002-09-18 09:04:55 +000093#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
95#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
96#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkab255f22002-09-18 09:04:55 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkab255f22002-09-18 09:04:55 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
101#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkab255f22002-09-18 09:04:55 +0000102
Stefan Roese550650d2010-09-20 16:05:31 +0200103#define CONFIG_CONS_INDEX 1 /* Use UART0 */
104#define CONFIG_SYS_NS16550
105#define CONFIG_SYS_NS16550_SERIAL
106#define CONFIG_SYS_NS16550_REG_SIZE 1
107#define CONFIG_SYS_NS16550_CLK get_serial_clock()
108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
wdenkab255f22002-09-18 09:04:55 +0000110
111/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000113 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
114 57600, 115200, 230400, 460800, 921600 }
wdenkab255f22002-09-18 09:04:55 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
117#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkab255f22002-09-18 09:04:55 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkab255f22002-09-18 09:04:55 +0000120
121#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
122
123/*-----------------------------------------------------------------------
124 * Start addresses for the final memory configuration
125 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkab255f22002-09-18 09:04:55 +0000127 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchsa00c1372010-07-26 17:17:52 +0200129#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
130#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
131#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkab255f22002-09-18 09:04:55 +0000133
134/*
135 * For booting Linux, the board info and command line data
136 * have to be in the first 8 MB of memory, since this is
137 * the maximum mapped by the Linux kernel during initialization.
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkab255f22002-09-18 09:04:55 +0000140/*-----------------------------------------------------------------------
141 * FLASH organization
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
144#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkab255f22002-09-18 09:04:55 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
147#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkab255f22002-09-18 09:04:55 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
150#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
151#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkab255f22002-09-18 09:04:55 +0000152/*
153 * The following defines are added for buggy IOP480 byte interface.
154 * All other boards should use the standard values (CPCI405 etc.)
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
157#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
158#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkab255f22002-09-18 09:04:55 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkab255f22002-09-18 09:04:55 +0000161
162#if 0 /* Use FLASH for environment variables */
163
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200164#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200165#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
166#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
wdenkab255f22002-09-18 09:04:55 +0000167
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200168#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
wdenkab255f22002-09-18 09:04:55 +0000169
170#else /* Use EEPROM for environment variables */
171
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200172#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200173#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
174#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000175 /* total size of a CAT24WC08 is 1024 bytes */
wdenkab255f22002-09-18 09:04:55 +0000176#endif
177
178/*-----------------------------------------------------------------------
179 * I2C EEPROM (CAT24WC08) for environment
180 */
wdenkc837dcb2004-01-20 23:12:12 +0000181#define CONFIG_HARD_I2C /* I2C with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200182#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
184#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkab255f22002-09-18 09:04:55 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
187#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenkab255f22002-09-18 09:04:55 +0000188/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
wdenkab255f22002-09-18 09:04:55 +0000190
wdenkab255f22002-09-18 09:04:55 +0000191/*
192 * Init Memory Controller:
193 *
194 * BR0/1 and OR0/1 (FLASH)
195 */
196
197#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
198#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
199
200/*-----------------------------------------------------------------------
201 * External Bus Controller (EBC) Setup
202 */
203
wdenkc837dcb2004-01-20 23:12:12 +0000204/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_EBC_PB0AP 0x92015480
206#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkab255f22002-09-18 09:04:55 +0000207
wdenkc837dcb2004-01-20 23:12:12 +0000208/* Memory Bank 1 (CAN/USB) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
210#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000211
wdenkc837dcb2004-01-20 23:12:12 +0000212/* Memory Bank 2 (Misc-IO/LEDs) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
214#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000215
wdenkc837dcb2004-01-20 23:12:12 +0000216/* Memory Bank 3 (CAN Features) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
218#define CONFIG_SYS_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
wdenkab255f22002-09-18 09:04:55 +0000219
220/*-----------------------------------------------------------------------
221 * Definitions for initial stack pointer and data area (in RAM)
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
224#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
225#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
226#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
227#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkab255f22002-09-18 09:04:55 +0000228
229
230/*
231 * Internal Definitions
232 *
233 * Boot Flags
234 */
235#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
236#define BOOTFLAG_WARM 0x02 /* Software reboot */
237
238#endif /* __CONFIG_H */