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Tim Schendekehl14c32612011-11-01 23:55:01 +00001/*
2 * (C) Copyright 2011
3 * egnite GmbH <info@egnite.de>
4 *
5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Tim Schendekehl14c32612011-11-01 23:55:01 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/hardware.h>
14
Tim Schendekehl6dbeb892014-06-12 17:25:36 +020015
Tim Schendekehl14c32612011-11-01 23:55:01 +000016/* The first stage boot loader expects u-boot running at this address. */
17#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
18
19/* The first stage boot loader takes care of low level initialization. */
20#define CONFIG_SKIP_LOWLEVEL_INIT
21
22/* Set our official architecture number. */
23#define MACH_TYPE_ETHERNUT5 1971
24#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
25
26/* CPU information */
Tim Schendekehl14c32612011-11-01 23:55:01 +000027#define CONFIG_DISPLAY_CPUINFO /* Display at console. */
28#define CONFIG_ARCH_CPU_INIT
29
30/* ARM asynchronous clock */
31#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
32#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl14c32612011-11-01 23:55:01 +000033
34/* 32kB internal SRAM */
35#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
36#define CONFIG_SRAM_SIZE (32 << 10)
Rob Herring3d6ba912012-07-13 09:44:01 +000037#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
38 GENERATED_GBL_DATA_SIZE)
Tim Schendekehl14c32612011-11-01 23:55:01 +000039
40/* 128MB SDRAM in 1 bank */
41#define CONFIG_NR_DRAM_BANKS 1
42#define CONFIG_SYS_SDRAM_BASE 0x20000000
43#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
44#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
45#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
46#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
47#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
48#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
49 - CONFIG_SYS_MALLOC_LEN)
50
51/* 512kB on-chip NOR flash */
52# define CONFIG_SYS_MAX_FLASH_BANKS 1
53# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
54# define CONFIG_AT91_EFLASH
55# define CONFIG_SYS_MAX_FLASH_SECT 32
56# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
57# define CONFIG_EFLASH_PROTSECTORS 1
58
59/* 512kB DataFlash at NPCS0 */
60#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
61#define CONFIG_HAS_DATAFLASH
Tim Schendekehl14c32612011-11-01 23:55:01 +000062#define CONFIG_ATMEL_DATAFLASH_SPI
63#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
64#define DATAFLASH_TCSS (0x1a << 16)
65#define DATAFLASH_TCHS (0x1 << 24)
66
67#define CONFIG_ENV_IS_IN_SPI_FLASH
68#define CONFIG_ENV_OFFSET 0x3DE000
69#define CONFIG_ENV_SECT_SIZE (132 << 10)
70#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
71#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
72 + CONFIG_ENV_OFFSET)
73#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
74 + 0x042000)
75
76/* SPI */
77#define CONFIG_ATMEL_SPI
Tim Schendekehl14c32612011-11-01 23:55:01 +000078#define AT91_SPI_CLK 15000000
79
80/* Serial port */
81#define CONFIG_ATMEL_USART
82#define CONFIG_USART3 /* USART 3 is DBGU */
83#define CONFIG_BAUDRATE 115200
Tim Schendekehl14c32612011-11-01 23:55:01 +000084#define CONFIG_USART_BASE ATMEL_BASE_DBGU
85#define CONFIG_USART_ID ATMEL_ID_SYS
86
87/* Misc. hardware drivers */
88#define CONFIG_AT91_GPIO
89
90/* Command line configuration */
Tim Schendekehl14c32612011-11-01 23:55:01 +000091#define CONFIG_CMD_JFFS2
92#define CONFIG_CMD_MII
93#define CONFIG_CMD_MTDPARTS
94#define CONFIG_CMD_NAND
95#define CONFIG_CMD_SPI
96
Joe Hershbergeref0f2f52015-06-22 16:15:30 -050097#ifndef MINIMAL_LOADER
Tim Schendekehl14c32612011-11-01 23:55:01 +000098#define CONFIG_CMD_ASKENV
99#define CONFIG_CMD_BSP
100#define CONFIG_CMD_CACHE
101#define CONFIG_CMD_CDP
102#define CONFIG_CMD_DATE
103#define CONFIG_CMD_DHCP
104#define CONFIG_CMD_DNS
105#define CONFIG_CMD_EXT2
106#define CONFIG_CMD_FAT
107#define CONFIG_CMD_I2C
108#define CONFIG_CMD_MMC
109#define CONFIG_CMD_PING
110#define CONFIG_CMD_RARP
111#define CONFIG_CMD_REISER
112#define CONFIG_CMD_SAVES
Tim Schendekehl14c32612011-11-01 23:55:01 +0000113#define CONFIG_CMD_SF
114#define CONFIG_CMD_SNTP
115#define CONFIG_CMD_UBI
116#define CONFIG_CMD_UBIFS
117#define CONFIG_CMD_UNZIP
118#define CONFIG_CMD_USB
119#endif
120
121/* NAND flash */
122#ifdef CONFIG_CMD_NAND
123#define CONFIG_SYS_MAX_NAND_DEVICE 1
124#define CONFIG_SYS_NAND_BASE 0x40000000
125#define CONFIG_SYS_NAND_DBW_8
126#define CONFIG_NAND_ATMEL
127/* our ALE is AD21 */
128#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
129/* our CLE is AD22 */
130#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100131#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000132#endif
133
134/* JFFS2 */
135#ifdef CONFIG_CMD_JFFS2
Tim Schendekehl14c32612011-11-01 23:55:01 +0000136#define CONFIG_JFFS2_CMDLINE
137#define CONFIG_JFFS2_NAND
138#endif
139
140/* Ethernet */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000141#define CONFIG_NET_RETRY_COUNT 20
142#define CONFIG_MACB
143#define CONFIG_RMII
144#define CONFIG_PHY_ID 0
145#define CONFIG_MACB_SEARCH_PHY
146
147/* MMC */
148#ifdef CONFIG_CMD_MMC
149#define CONFIG_MMC
150#define CONFIG_GENERIC_MMC
151#define CONFIG_GENERIC_ATMEL_MCI
152#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
153#endif
154
155/* USB */
156#ifdef CONFIG_CMD_USB
157#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800158#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Tim Schendekehl14c32612011-11-01 23:55:01 +0000159#define CONFIG_USB_OHCI_NEW
160#define CONFIG_SYS_USB_OHCI_CPU_INIT
161#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
162#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
163#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
164#define CONFIG_USB_STORAGE
165#endif
166
167/* RTC */
168#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
169#define CONFIG_RTC_PCF8563
170#define CONFIG_SYS_I2C_RTC_ADDR 0x51
171#endif
172
173/* I2C */
174#define CONFIG_SYS_MAX_I2C_BUS 1
Tim Schendekehl14c32612011-11-01 23:55:01 +0000175
Heiko Schocherea818db2013-01-29 08:53:15 +0100176#define CONFIG_SYS_I2C
177#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
178#define CONFIG_SYS_I2C_SOFT_SPEED 100000
179#define CONFIG_SYS_I2C_SOFT_SLAVE 0
180
Tim Schendekehl14c32612011-11-01 23:55:01 +0000181#define I2C_SOFT_DECLARATIONS
182
183#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
184#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
185
186#define I2C_INIT { \
187 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
188 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
189 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
190 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
191 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
192}
193
194#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
195#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
196#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
197#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
198#define I2C_DELAY udelay(100)
199#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
200
201/* DHCP/BOOTP options */
202#ifdef CONFIG_CMD_DHCP
203#define CONFIG_BOOTP_BOOTFILESIZE
204#define CONFIG_BOOTP_BOOTPATH
205#define CONFIG_BOOTP_GATEWAY
206#define CONFIG_BOOTP_HOSTNAME
207#define CONFIG_SYS_AUTOLOAD "n"
208#endif
209
210/* File systems */
211#define CONFIG_MTD_DEVICE
212#define CONFIG_MTD_PARTITIONS
213#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
214#define MTDIDS_DEFAULT "nand0=atmel_nand"
215#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
216#endif
217#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
218 defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
219#define CONFIG_DOS_PARTITION
220#endif
221#define CONFIG_LZO
222#define CONFIG_RBTREE
223
224/* Boot command */
225#define CONFIG_BOOTDELAY 3
226#define CONFIG_CMDLINE_TAG
227#define CONFIG_SETUP_MEMORY_TAGS
228#define CONFIG_INITRD_TAG
229#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
230#if defined(CONFIG_CMD_NAND)
231#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
232 "root=/dev/mtdblock0 " \
233 MTDPARTS_DEFAULT \
234 " rw rootfstype=jffs2"
235#endif
236
237/* Misc. u-boot settings */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000238#define CONFIG_SYS_HUSH_PARSER
Tim Schendekehl14c32612011-11-01 23:55:01 +0000239#define CONFIG_SYS_CBSIZE 256
240#define CONFIG_SYS_MAXARGS 16
241#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
242 + sizeof(CONFIG_SYS_PROMPT))
243#define CONFIG_SYS_LONGHELP
244#define CONFIG_CMDLINE_EDITING
245
246#endif