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wdenk63f34912004-01-02 15:01:32 +00001/*
2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
3 *
4 * Masami Komiya (mkomiya@sonare.it)
5 *
6 * Most part is taken from rtl8139.c of etherboot
7 *
8 */
9
10/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
11
12 ported from the linux driver written by Donald Becker
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
14
15 This software may be used and distributed according to the terms
16 of the GNU Public License, incorporated herein by reference.
17
18 changes to the original driver:
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
21
22*/
23
24/*********************************************************************/
25/* Revision History */
26/*********************************************************************/
27
28/*
29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
30 Put in virt_to_bus calls to allow Etherboot relocation.
31
32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
34 NIC remains live and can crash the kernel later.
35
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37 Shuffled things around, removed the leftovers from the 8129 support
38 that was in the Linux driver and added a bit more 8139 definitions.
39 Moved the 8K receive buffer to a fixed, available address outside the
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
41 way to make room for the Etherboot features that need substantial amounts
42 of code like the ANSI console support. Currently the buffer is just below
43 0x10000, so this even conforms to the tagged boot image specification,
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
45 interpretation of this "reserved" is that Etherboot may do whatever it
46 likes, as long as its environment is kept intact (like the BIOS
wdenkb6e4c402004-01-02 16:05:07 +000047 variables). Hopefully fixed rtl_poll() once and for all. The symptoms
wdenk63f34912004-01-02 15:01:32 +000048 were that if Etherboot was left at the boot menu for several minutes, the
49 first eth_poll failed. Seems like I am the only person who does this.
50 First of all I fixed the debugging code and then set out for a long bug
51 hunting session. It took me about a week full time work - poking around
52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53 driver and even the FreeBSD driver (what a piece of crap!) - and
54 eventually spotted the nasty thing: the transmit routine was acknowledging
55 each and every interrupt pending, including the RxOverrun and RxFIFIOver
wdenkb6e4c402004-01-02 16:05:07 +000056 interrupts. This confused the RTL8139 thoroughly. It destroyed the
wdenk63f34912004-01-02 15:01:32 +000057 Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58 get the next packet. Oh well, what fun.
59
wdenkb6e4c402004-01-02 16:05:07 +000060 18 Jan 2000 mdc@thinguin.org (Marty Connor)
wdenk63f34912004-01-02 15:01:32 +000061 Drastically simplified error handling. Basically, if any error
62 in transmission or reception occurs, the card is reset.
63 Also, pointed all transmit descriptors to the same buffer to
wdenkb6e4c402004-01-02 16:05:07 +000064 save buffer space. This should decrease driver size and avoid
wdenk63f34912004-01-02 15:01:32 +000065 corruption because of exceeding 32K during runtime.
66
wdenkb6e4c402004-01-02 16:05:07 +000067 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
wdenk63f34912004-01-02 15:01:32 +000068 rtl_poll was quite broken: it used the RxOK interrupt flag instead
69 of the RxBufferEmpty flag which often resulted in very bad
70 transmission performace - below 1kBytes/s.
71
72*/
73
74#include <common.h>
75#include <malloc.h>
76#include <net.h>
Ben Warren0b252f52008-08-31 21:41:08 -070077#include <netdev.h>
wdenk63f34912004-01-02 15:01:32 +000078#include <asm/io.h>
79#include <pci.h>
80
Shinya Kuribayashid1276c72008-01-16 16:11:14 +090081#define RTL_TIMEOUT 100000
wdenk63f34912004-01-02 15:01:32 +000082
83#define ETH_FRAME_LEN 1514
84#define ETH_ALEN 6
85#define ETH_ZLEN 60
86
87/* PCI Tuning Parameters
88 Threshold is bytes transferred to chip before transmission starts. */
wdenkb6e4c402004-01-02 16:05:07 +000089#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
90#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
91#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
92#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
93#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
wdenk63f34912004-01-02 15:01:32 +000094#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
95#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
96#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
97
98#undef DEBUG_TX
99#undef DEBUG_RX
100
101#define currticks() get_timer(0)
wdenkb6e4c402004-01-02 16:05:07 +0000102#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
103#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
wdenk63f34912004-01-02 15:01:32 +0000104
105/* Symbolic offsets to registers. */
106enum RTL8139_registers {
107 MAC0=0, /* Ethernet hardware address. */
108 MAR0=8, /* Multicast filter. */
109 TxStatus0=0x10, /* Transmit status (four 32bit registers). */
110 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
111 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
112 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
113 IntrMask=0x3C, IntrStatus=0x3E,
114 TxConfig=0x40, RxConfig=0x44,
115 Timer=0x48, /* general-purpose counter. */
116 RxMissed=0x4C, /* 24 bits valid, write clears. */
117 Cfg9346=0x50, Config0=0x51, Config1=0x52,
118 TimerIntrReg=0x54, /* intr if gp counter reaches this value */
119 MediaStatus=0x58,
120 Config3=0x59,
121 MultiIntr=0x5C,
122 RevisionID=0x5E, /* revision of the RTL8139 chip */
123 TxSummary=0x60,
124 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
125 NWayExpansion=0x6A,
126 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
127 NWayTestReg=0x70,
128 RxCnt=0x72, /* packet received counter */
129 CSCR=0x74, /* chip status and configuration register */
130 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
131 /* from 0x84 onwards are a number of power management/wakeup frame
132 * definitions we will probably never need to know about. */
133};
134
135enum ChipCmdBits {
136 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
137
138/* Interrupt register bits, using my own meaningful names. */
139enum IntrStatusBits {
140 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
141 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
142 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
143};
144enum TxStatusBits {
145 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
146 TxOutOfWindow=0x20000000, TxAborted=0x40000000,
147 TxCarrierLost=0x80000000,
148};
149enum RxStatusBits {
150 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
151 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
152 RxBadAlign=0x0002, RxStatusOK=0x0001,
153};
154
155enum MediaStatusBits {
156 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
157 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
158};
159
160enum MIIBMCRBits {
161 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
162 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
163};
164
165enum CSCRBits {
166 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
167 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
168 CSCR_LinkDownCmd=0x0f3c0,
169};
170
171/* Bits in RxConfig. */
172enum rx_mode_bits {
173 RxCfgWrap=0x80,
174 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
175 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
176};
177
178static int ioaddr;
179static unsigned int cur_rx,cur_tx;
180
181/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
182static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
183static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
184
185static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
186static int read_eeprom(int location, int addr_len);
187static void rtl_reset(struct eth_device *dev);
188static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
189static int rtl_poll(struct eth_device *dev);
190static void rtl_disable(struct eth_device *dev);
David Updegraff53a5c422007-06-11 10:41:07 -0500191#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
Wolfgang Denk85eb5ca2007-08-14 09:47:27 +0200192static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
193{
194 return (0);
195}
David Updegraff53a5c422007-06-11 10:41:07 -0500196#endif
wdenk63f34912004-01-02 15:01:32 +0000197
198static struct pci_device_id supported[] = {
199 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
Jin Zhengxiongda012ab2006-06-28 08:43:56 -0500200 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
wdenk63f34912004-01-02 15:01:32 +0000201 {}
202};
203
204int rtl8139_initialize(bd_t *bis)
205{
206 pci_dev_t devno;
207 int card_number = 0;
208 struct eth_device *dev;
209 u32 iobase;
210 int idx=0;
211
212 while(1){
213 /* Find RTL8139 */
214 if ((devno = pci_find_devices(supported, idx++)) < 0)
215 break;
216
217 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
218 iobase &= ~0xf;
219
220 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
221
222 dev = (struct eth_device *)malloc(sizeof *dev);
223
224 sprintf (dev->name, "RTL8139#%d", card_number);
225
226 dev->priv = (void *) devno;
227 dev->iobase = (int)bus_to_phys(iobase);
228 dev->init = rtl8139_probe;
229 dev->halt = rtl_disable;
230 dev->send = rtl_transmit;
231 dev->recv = rtl_poll;
David Updegraff53a5c422007-06-11 10:41:07 -0500232#ifdef CONFIG_MCAST_TFTP
233 dev->mcast = rtl_bcast_addr;
234#endif
wdenk63f34912004-01-02 15:01:32 +0000235
236 eth_register (dev);
237
238 card_number++;
239
240 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
241
242 udelay (10 * 1000);
243 }
244
245 return card_number;
246}
247
248static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
249{
250 int i;
251 int speed10, fullduplex;
252 int addr_len;
253 unsigned short *ap = (unsigned short *)dev->enetaddr;
254
255 ioaddr = dev->iobase;
256
257 /* Bring the chip out of low-power mode. */
258 outb(0x00, ioaddr + Config1);
259
260 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
261 for (i = 0; i < 3; i++)
wdenk756f5862005-04-03 15:51:42 +0000262 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
wdenk63f34912004-01-02 15:01:32 +0000263
264 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
265 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
266
267 rtl_reset(dev);
268
269 if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
270 printf("Cable not connected or other link failure\n");
Ben Warren422b1a02008-01-09 18:15:53 -0500271 return -1 ;
wdenk63f34912004-01-02 15:01:32 +0000272 }
273
Ben Warren422b1a02008-01-09 18:15:53 -0500274 return 0;
wdenk63f34912004-01-02 15:01:32 +0000275}
276
277/* Serial EEPROM section. */
278
279/* EEPROM_Ctrl bits. */
wdenkb6e4c402004-01-02 16:05:07 +0000280#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
281#define EE_CS 0x08 /* EEPROM chip select. */
282#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
283#define EE_WRITE_0 0x00
284#define EE_WRITE_1 0x02
285#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
wdenk63f34912004-01-02 15:01:32 +0000286#define EE_ENB (0x80 | EE_CS)
287
288/*
289 Delay between EEPROM clock transitions.
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200290 No extra delay is needed with 33MHz PCI, but 66MHz may change this.
wdenk63f34912004-01-02 15:01:32 +0000291*/
292
wdenkb6e4c402004-01-02 16:05:07 +0000293#define eeprom_delay() inl(ee_addr)
wdenk63f34912004-01-02 15:01:32 +0000294
295/* The EEPROM commands include the alway-set leading bit. */
wdenkb6e4c402004-01-02 16:05:07 +0000296#define EE_WRITE_CMD (5)
297#define EE_READ_CMD (6)
298#define EE_ERASE_CMD (7)
wdenk63f34912004-01-02 15:01:32 +0000299
300static int read_eeprom(int location, int addr_len)
301{
302 int i;
303 unsigned int retval = 0;
304 long ee_addr = ioaddr + Cfg9346;
305 int read_cmd = location | (EE_READ_CMD << addr_len);
306
307 outb(EE_ENB & ~EE_CS, ee_addr);
308 outb(EE_ENB, ee_addr);
309 eeprom_delay();
310
311 /* Shift the read command bits out. */
312 for (i = 4 + addr_len; i >= 0; i--) {
313 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
314 outb(EE_ENB | dataval, ee_addr);
315 eeprom_delay();
316 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
317 eeprom_delay();
318 }
319 outb(EE_ENB, ee_addr);
320 eeprom_delay();
321
322 for (i = 16; i > 0; i--) {
323 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
324 eeprom_delay();
325 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
326 outb(EE_ENB, ee_addr);
327 eeprom_delay();
328 }
329
330 /* Terminate the EEPROM access. */
331 outb(~EE_CS, ee_addr);
332 eeprom_delay();
333 return retval;
334}
335
336static const unsigned int rtl8139_rx_config =
337 (RX_BUF_LEN_IDX << 11) |
338 (RX_FIFO_THRESH << 13) |
339 (RX_DMA_BURST << 8);
340
341static void set_rx_mode(struct eth_device *dev) {
342 unsigned int mc_filter[2];
343 int rx_mode;
344 /* !IFF_PROMISC */
345 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
346 mc_filter[1] = mc_filter[0] = 0xffffffff;
347
348 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
349
350 outl(mc_filter[0], ioaddr + MAR0 + 0);
351 outl(mc_filter[1], ioaddr + MAR0 + 4);
352}
353
354static void rtl_reset(struct eth_device *dev)
355{
356 int i;
357
358 outb(CmdReset, ioaddr + ChipCmd);
359
360 cur_rx = 0;
361 cur_tx = 0;
362
363 /* Give the chip 10ms to finish the reset. */
364 for (i=0; i<100; ++i){
365 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
366 udelay (100); /* wait 100us */
367 }
368
369
370 for (i = 0; i < ETH_ALEN; i++)
371 outb(dev->enetaddr[i], ioaddr + MAC0 + i);
372
373 /* Must enable Tx/Rx before setting transfer thresholds! */
374 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
375 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
376 ioaddr + RxConfig); /* accept no frames yet! */
377 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
378
379 /* The Linux driver changes Config1 here to use a different LED pattern
380 * for half duplex or full/autodetect duplex (for full/autodetect, the
381 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
382 * TX/RX, Link100, Link10). This is messy, because it doesn't match
383 * the inscription on the mounting bracket. It should not be changed
384 * from the configuration EEPROM default, because the card manufacturer
385 * should have set that to match the card. */
386
387#ifdef DEBUG_RX
388 printf("rx ring address is %X\n",(unsigned long)rx_ring);
389#endif
Shinya Kuribayashi96a23672008-01-16 16:12:26 +0900390 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
wdenk63f34912004-01-02 15:01:32 +0000391 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
392
393 /* If we add multicast support, the MAR0 register would have to be
394 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
wdenkb6e4c402004-01-02 16:05:07 +0000395 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
wdenk63f34912004-01-02 15:01:32 +0000396
397 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
398
399 outl(rtl8139_rx_config, ioaddr + RxConfig);
400
401 /* Start the chip's Tx and Rx process. */
402 outl(0, ioaddr + RxMissed);
403
404 /* set_rx_mode */
405 set_rx_mode(dev);
406
407 /* Disable all known interrupts by setting the interrupt mask. */
408 outw(0, ioaddr + IntrMask);
409}
410
411static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
412{
Shinya Kuribayashid1276c72008-01-16 16:11:14 +0900413 unsigned int status;
wdenk63f34912004-01-02 15:01:32 +0000414 unsigned long txstatus;
415 unsigned int len = length;
Shinya Kuribayashid1276c72008-01-16 16:11:14 +0900416 int i = 0;
wdenk63f34912004-01-02 15:01:32 +0000417
418 ioaddr = dev->iobase;
419
420 memcpy((char *)tx_buffer, (char *)packet, (int)length);
421
422#ifdef DEBUG_TX
423 printf("sending %d bytes\n", len);
424#endif
425
426 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
427 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
428 while (len < ETH_ZLEN) {
429 tx_buffer[len++] = '\0';
430 }
431
Shinya Kuribayashi96a23672008-01-16 16:12:26 +0900432 flush_cache((unsigned long)tx_buffer, length);
wdenk63f34912004-01-02 15:01:32 +0000433 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
434 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
435 ioaddr + TxStatus0 + cur_tx*4);
436
wdenk63f34912004-01-02 15:01:32 +0000437 do {
438 status = inw(ioaddr + IntrStatus);
439 /* Only acknlowledge interrupt sources we can properly handle
440 * here - the RxOverflow/RxFIFOOver MUST be handled in the
wdenkb6e4c402004-01-02 16:05:07 +0000441 * rtl_poll() function. */
wdenk63f34912004-01-02 15:01:32 +0000442 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
443 if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
Shinya Kuribayashid1276c72008-01-16 16:11:14 +0900444 udelay(10);
445 } while (i++ < RTL_TIMEOUT);
wdenk63f34912004-01-02 15:01:32 +0000446
447 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
448
449 if (status & TxOK) {
450 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
451#ifdef DEBUG_TX
452 printf("tx done (%d ticks), status %hX txstatus %X\n",
453 to-currticks(), status, txstatus);
454#endif
455 return length;
456 } else {
457#ifdef DEBUG_TX
Shinya Kuribayashid1276c72008-01-16 16:11:14 +0900458 printf("tx timeout/error (%d usecs), status %hX txstatus %X\n",
459 10*i, status, txstatus);
wdenk63f34912004-01-02 15:01:32 +0000460#endif
461 rtl_reset(dev);
462
463 return 0;
464 }
465}
466
467static int rtl_poll(struct eth_device *dev)
468{
469 unsigned int status;
470 unsigned int ring_offs;
471 unsigned int rx_size, rx_status;
472 int length=0;
473
474 ioaddr = dev->iobase;
475
476 if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
477 return 0;
478 }
479
480 status = inw(ioaddr + IntrStatus);
481 /* See below for the rest of the interrupt acknowledges. */
482 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
483
484#ifdef DEBUG_RX
485 printf("rtl_poll: int %hX ", status);
486#endif
487
488 ring_offs = cur_rx % RX_BUF_LEN;
Shinya Kuribayashi96a23672008-01-16 16:12:26 +0900489 /* ring_offs is guaranteed being 4-byte aligned */
Shinya Kuribayashic2f896b2008-01-16 16:13:31 +0900490 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
wdenk63f34912004-01-02 15:01:32 +0000491 rx_size = rx_status >> 16;
492 rx_status &= 0xffff;
493
494 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
495 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
496 printf("rx error %hX\n", rx_status);
wdenkb6e4c402004-01-02 16:05:07 +0000497 rtl_reset(dev); /* this clears all interrupts still pending */
wdenk63f34912004-01-02 15:01:32 +0000498 return 0;
499 }
500
501 /* Received a good packet */
502 length = rx_size - 4; /* no one cares about the FCS */
503 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
504 int semi_count = RX_BUF_LEN - ring_offs - 4;
505 unsigned char rxdata[RX_BUF_LEN];
506
507 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
508 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
509
510 NetReceive(rxdata, length);
511#ifdef DEBUG_RX
512 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
513#endif
514 } else {
515 NetReceive(rx_ring + ring_offs + 4, length);
516#ifdef DEBUG_RX
517 printf("rx packet %d bytes", rx_size-4);
518#endif
519 }
Shinya Kuribayashi96a23672008-01-16 16:12:26 +0900520 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
wdenk63f34912004-01-02 15:01:32 +0000521
522 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
523 outw(cur_rx - 16, ioaddr + RxBufPtr);
524 /* See RTL8139 Programming Guide V0.1 for the official handling of
525 * Rx overflow situations. The document itself contains basically no
526 * usable information, except for a few exception handling rules. */
527 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
528 return length;
529}
530
531static void rtl_disable(struct eth_device *dev)
532{
533 int i;
534
wdenkb6e4c402004-01-02 16:05:07 +0000535 ioaddr = dev->iobase;
536
wdenk63f34912004-01-02 15:01:32 +0000537 /* reset the chip */
538 outb(CmdReset, ioaddr + ChipCmd);
539
540 /* Give the chip 10ms to finish the reset. */
541 for (i=0; i<100; ++i){
542 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
543 udelay (100); /* wait 100us */
544 }
545}