blob: df7eb05e82460e998be15e56734e8ff8ff83f5e3 [file] [log] [blame]
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +01001/*
2 * Copyright (C) 2004-2007 ARM Limited.
3 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * As a special exception, if other files instantiate templates or use macros
19 * or inline functions from this file, or you compile this file and link it
20 * with other works to produce a work based on this file, this file does not
21 * by itself cause the resulting work to be covered by the GNU General Public
22 * License. However the source code for this file must still be made available
23 * in accordance with section (3) of the GNU General Public License.
24
25 * This exception does not invalidate any other reasons why a work based on
26 * this file might be covered by the GNU General Public License.
27 */
28
29#include <common.h>
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +053030#include <serial.h>
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010031
Alexander Merklefd602c52015-03-19 18:37:19 +010032#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010033/*
Alexander Merklefd602c52015-03-19 18:37:19 +010034 * ARMV6 & ARMV7
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010035 */
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020036#define DCC_RBIT (1 << 30)
37#define DCC_WBIT (1 << 29)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010038
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020039#define write_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010040 __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
41
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020042#define read_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010043 __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
44
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020045#define status_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010046 __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
47
Jean-Christophe PLAGNIOL-VILLARD65a76d42009-05-15 23:47:14 +020048#elif defined(CONFIG_CPU_XSCALE)
49/*
50 * XSCALE
51 */
52#define DCC_RBIT (1 << 31)
53#define DCC_WBIT (1 << 28)
54
55#define write_dcc(x) \
56 __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
57
58#define read_dcc(x) \
59 __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
60
61#define status_dcc(x) \
62 __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
63
Siva Durga Prasad Paladugue05412f2015-05-29 09:54:37 +020064#elif defined(CONFIG_CPU_ARMV8)
65/*
66 * ARMV8
67 */
68#define DCC_RBIT (1 << 30)
69#define DCC_WBIT (1 << 29)
70
71#define write_dcc(x) \
72 __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x))
73
74#define read_dcc(x) \
75 __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x))
76
77#define status_dcc(x) \
78 __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x))
79
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020080#else
81#define DCC_RBIT (1 << 0)
82#define DCC_WBIT (1 << 1)
83
84#define write_dcc(x) \
85 __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
86
87#define read_dcc(x) \
88 __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
89
90#define status_dcc(x) \
91 __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
92
93#endif
94
95#define can_read_dcc(x) do { \
96 status_dcc(x); \
97 x &= DCC_RBIT; \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010098 } while (0);
99
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200100#define can_write_dcc(x) do { \
101 status_dcc(x); \
102 x &= DCC_WBIT; \
103 x = (x == 0); \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100104 } while (0);
105
106#define TIMEOUT_COUNT 0x4000000
107
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530108static int arm_dcc_init(void)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100109{
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100110 return 0;
111}
112
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530113static int arm_dcc_getc(void)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100114{
115 int ch;
116 register unsigned int reg;
117
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200118 do {
119 can_read_dcc(reg);
120 } while (!reg);
121 read_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100122
123 return ch;
124}
125
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530126static void arm_dcc_putc(char ch)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100127{
128 register unsigned int reg;
129 unsigned int timeout_count = TIMEOUT_COUNT;
130
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200131 while (--timeout_count) {
132 can_write_dcc(reg);
133 if (reg)
134 break;
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100135 }
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200136 if (timeout_count == 0)
137 return;
138 else
139 write_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100140}
141
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530142static int arm_dcc_tstc(void)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100143{
144 register unsigned int reg;
145
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200146 can_read_dcc(reg);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100147
148 return reg;
149}
150
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530151static void arm_dcc_setbrg(void)
152{
153}
154
155static struct serial_device arm_dcc_drv = {
156 .name = "arm_dcc",
157 .start = arm_dcc_init,
158 .stop = NULL,
159 .setbrg = arm_dcc_setbrg,
160 .putc = arm_dcc_putc,
Axel Lin012a2c12013-08-17 15:39:34 +0800161 .puts = default_serial_puts,
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530162 .getc = arm_dcc_getc,
163 .tstc = arm_dcc_tstc,
164};
165
166void arm_dcc_initialize(void)
167{
168 serial_register(&arm_dcc_drv);
169}
170
Michal Simeke70fb532013-01-22 23:40:06 +0000171__weak struct serial_device *default_serial_console(void)
172{
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530173 return &arm_dcc_drv;
Michal Simeke70fb532013-01-22 23:40:06 +0000174}