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wdenk5b1d7132002-11-03 00:07:02 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia io remapping
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
17 * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
18 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
19*/
20
21#define CFG_PCMCIA_IO_ADDR 0xff020000
22#define CFG_PCMCIA_IO_SIZE 0x10000
23#define CFG_PCMCIA_MEM_ADDR 0xe0000000
24#define CFG_PCMCIA_MEM_SIZE 0x10000
25#define CFG_IMMR 0xFF000000
wdenk2535d602003-07-17 23:16:40 +000026#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
wdenk5b1d7132002-11-03 00:07:02 +000027#define CFG_SDRAM_BASE 0x00000000
28#define CFG_FLASH_BASE 0x02800000
29#define BCSR_ADDR ((uint) 0xff010000)
30#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
31
32/* ------------------------------------------------------------------------- */
33
34/*
35 * board/config.h - configuration options, board specific
36 */
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
41#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
42#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
43
44#define CONFIG_VIDEO 1 /* To enable video controller support */
45#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
46#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
47#define CFG_I2C_SLAVE 0x7F
48
wdenk5b1d7132002-11-03 00:07:02 +000049/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
50
51/* Video related */
52
53#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
54#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
55#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
56#define CONFIG_VIDEO_SIZE (2*1024*1024)
57/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
58
59/* Wireless 56Khz 4PPM keyboard on SMCx */
60
wdenk682011f2003-06-03 23:54:09 +000061/*#define CONFIG_KEYBOARD 1 */
wdenk5b1d7132002-11-03 00:07:02 +000062#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
63
64/*
65 * High Level Configuration Options
66 * (easy to change)
67 */
wdenk5b1d7132002-11-03 00:07:02 +000068#define CONFIG_MPC823 1
69#define CONFIG_MPC823FADS 1
70#define CONFIG_FADS 1
71
72#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
73#undef CONFIG_8xx_CONS_SMC2
74#undef CONFIG_8xx_CONS_NONE
75#define CONFIG_BAUDRATE 115200
76
77/* Set the CPU speed to 50Mhz on the FADS */
78
79#if 0
80#define MPC8XX_FACT 10 /* Multiply by 10 */
81#define MPC8XX_XIN 5000000 /* 5 MHz in */
82#else
83#define MPC8XX_FACT 10 /* Multiply by 10 */
84#define MPC8XX_XIN 5000000 /* 5 MHz in */
85#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
86#endif
87#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
88
89#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
90
91#if 1
92#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
93#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
94#define CONFIG_BOOTARGS ""
95#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020096"bootp ;" \
97"setenv bootargs console=tty0 console=ttyS0 " \
98"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
99"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
wdenk5b1d7132002-11-03 00:07:02 +0000100"bootm"
101#else
102#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
103#endif
104
105#undef CONFIG_WATCHDOG /* watchdog disabled */
106
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500107
108/*
109 * BOOTP options
110 */
111#define CONFIG_BOOTP_SUBNETMASK
112#define CONFIG_BOOTP_GATEWAY
113#define CONFIG_BOOTP_HOSTNAME
114#define CONFIG_BOOTP_BOOTPATH
115#define CONFIG_BOOTP_BOOTFILESIZE
116#define CONFIG_BOOTP_SUBNETMASK
117#define CONFIG_BOOTP_GATEWAY
118#define CONFIG_BOOTP_HOSTNAME
119#define CONFIG_BOOTP_NISDOMAIN
120#define CONFIG_BOOTP_BOOTPATH
121#define CONFIG_BOOTP_DNS
122#define CONFIG_BOOTP_DNS2
123#define CONFIG_BOOTP_SEND_HOSTNAME
124#define CONFIG_BOOTP_NTPSERVER
125#define CONFIG_BOOTP_TIMEOFFSET
126
wdenk5b1d7132002-11-03 00:07:02 +0000127
Jon Loeliger60a08762007-07-07 21:04:26 -0500128/*
129 * Command line configuration.
130 */
131#include <config_cmd_default.h>
132
wdenk5b1d7132002-11-03 00:07:02 +0000133
134/*
135 * Miscellaneous configurable options
136 */
137#define CFG_LONGHELP /* undef to save memory */
138#define CFG_PROMPT ":>" /* Monitor Command Prompt */
Jon Loeliger60a08762007-07-07 21:04:26 -0500139#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000140#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
141#else
142#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
143#endif
144#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
145#define CFG_MAXARGS 16 /* max number of command args */
146#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
147
148#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
149#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
150
151#define CFG_LOAD_ADDR 0x00100000 /* default load address */
152
153#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
154
155#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
156
157/*
158 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here.
161 */
162/*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
164 */
165#define CFG_IMMR_SIZE ((uint)(64 * 1024))
166
167/*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM)
169 */
170#define CFG_INIT_RAM_ADDR CFG_IMMR
171#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
172#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
173#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175
176/*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
179 * Please note that CFG_SDRAM_BASE _must_ start at 0
180 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
181 */
182#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
183#if 0
184#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
185#else
186#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
187#endif
188#define CFG_MONITOR_BASE CFG_FLASH_BASE
189#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
190
191/*
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization.
195 */
196#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
197/*-----------------------------------------------------------------------
198 * FLASH organization
199 */
200#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
201#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
202
203#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
204#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
205
206#define CFG_ENV_IS_IN_FLASH 1
207#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
208#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200209#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk5b1d7132002-11-03 00:07:02 +0000210
211/*-----------------------------------------------------------------------
212 * Cache Configuration
213 */
214#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500215#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000216#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
217#endif
218
219/*-----------------------------------------------------------------------
220 * SYPCR - System Protection Control 11-9
221 * SYPCR can only be written once after reset!
222 *-----------------------------------------------------------------------
223 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
224 */
225#if defined(CONFIG_WATCHDOG)
226#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
227 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
228#else
229#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
230#endif
231
232/*-----------------------------------------------------------------------
233 * SIUMCR - SIU Module Configuration 11-6
234 *-----------------------------------------------------------------------
235 * PCMCIA config., multi-function pin tri-state
236 */
237#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
238
239/*-----------------------------------------------------------------------
240 * TBSCR - Time Base Status and Control 11-26
241 *-----------------------------------------------------------------------
242 * Clear Reference Interrupt Status, Timebase freezing enabled
243 */
244#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
245
246/*-----------------------------------------------------------------------
247 * PISCR - Periodic Interrupt Status and Control 11-31
248 *-----------------------------------------------------------------------
249 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
250 */
251#define CFG_PISCR (PISCR_PS | PISCR_PITF)
252
253/*-----------------------------------------------------------------------
254 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
255 *-----------------------------------------------------------------------
256 * Reset PLL lock status sticky bit, timer expired status bit and timer *
257 * interrupt status bit - leave PLL multiplication factor unchanged !
258 */
259#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
260
261/*-----------------------------------------------------------------------
262 * SCCR - System Clock and reset Control Register 15-27
263 *-----------------------------------------------------------------------
264 * Set clock output, timebase and RTC source and divider,
265 * power management and some other internal clocks
266 */
267#define SCCR_MASK SCCR_EBDF11
268#define CFG_SCCR (SCCR_TBS | \
269 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
270 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
271 SCCR_DFALCD00)
272
273 /*-----------------------------------------------------------------------
274 *
275 *-----------------------------------------------------------------------
276 *
277 */
278#define CFG_DER 0
279
280/* Because of the way the 860 starts up and assigns CS0 the
281* entire address space, we have to set the memory controller
282* differently. Normally, you write the option register
283* first, and then enable the chip select by writing the
284* base register. For CS0, you must write the base register
285* first, followed by the option register.
286*/
287
288/*
289 * Init Memory Controller:
290 *
291 * BR0/1 and OR0/1 (FLASH)
292 */
293/* the other CS:s are determined by looking at parameters in BCSRx */
294
295#define BCSR_SIZE ((uint)(64 * 1024))
296
297#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
298
299#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
300#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
301
302/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
303#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
304
305#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
306#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
307#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
308
309/* BCSRx - Board Control and Status Registers */
310#define CFG_OR1_REMAP CFG_OR0_REMAP
311#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
312#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
313
314
315/*
316 * Memory Periodic Timer Prescaler
317 */
318
319/* periodic timer for refresh */
320#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
321
322/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
323#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
324#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
325
326/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
327#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
328#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
329
330/*
331 * MAMR settings for SDRAM
332 */
333
334/* 8 column SDRAM */
335#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
336 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
337 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
338/* 9 column SDRAM */
339#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
340 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
341 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
342
343#define CFG_MAMR 0x13a01114
344/*
345 * Internal Definitions
346 *
347 * Boot Flags
348 */
349#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
350#define BOOTFLAG_WARM 0x02 /* Software reboot */
351
352/* values according to the manual */
353
354#define BCSR0 ((uint) (BCSR_ADDR + 00))
355#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
356#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
357#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
358#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
359
360/* FADS bitvalues by Helmut Buchsbaum
361 * see MPC8xxADS User's Manual for a proper description
362 * of the following structures
363 */
364
365#define BCSR0_ERB ((uint)0x80000000)
366#define BCSR0_IP ((uint)0x40000000)
367#define BCSR0_BDIS ((uint)0x10000000)
368#define BCSR0_BPS_MASK ((uint)0x0C000000)
369#define BCSR0_ISB_MASK ((uint)0x01800000)
370#define BCSR0_DBGC_MASK ((uint)0x00600000)
371#define BCSR0_DBPC_MASK ((uint)0x00180000)
372#define BCSR0_EBDF_MASK ((uint)0x00060000)
373
374#define BCSR1_FLASH_EN ((uint)0x80000000)
375#define BCSR1_DRAM_EN ((uint)0x40000000)
376#define BCSR1_ETHEN ((uint)0x20000000)
377#define BCSR1_IRDEN ((uint)0x10000000)
378#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
379#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
380#define BCSR1_BCSR_EN ((uint)0x02000000)
381#define BCSR1_RS232EN_1 ((uint)0x01000000)
382#define BCSR1_PCCEN ((uint)0x00800000)
383#define BCSR1_PCCVCC0 ((uint)0x00400000)
384#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
385#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
386#define BCSR1_RS232EN_2 ((uint)0x00040000)
387#define BCSR1_SDRAM_EN ((uint)0x00020000)
388#define BCSR1_PCCVCC1 ((uint)0x00010000)
389
390#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenkb54d32b2004-06-10 21:34:36 +0000391#define BCSR2_FLASH_PD_SHIFT 28
wdenk5b1d7132002-11-03 00:07:02 +0000392#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
wdenkb54d32b2004-06-10 21:34:36 +0000393#define BCSR2_DRAM_PD_SHIFT 23
wdenk5b1d7132002-11-03 00:07:02 +0000394#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
395#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
396
397#define BCSR3_DBID_MASK ((ushort)0x3800)
398#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
399#define BCSR3_BREVNR0 ((ushort)0x0080)
400#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
401#define BCSR3_BREVN1 ((ushort)0x0008)
402#define BCSR3_BREVN2_MASK ((ushort)0x0003)
403
404#define BCSR4_ETHLOOP ((uint)0x80000000)
405#define BCSR4_TFPLDL ((uint)0x40000000)
406#define BCSR4_TPSQEL ((uint)0x20000000)
407#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
408#ifdef CONFIG_MPC823
409#define BCSR4_USB_EN ((uint)0x08000000)
410#endif /* CONFIG_MPC823 */
411#ifdef CONFIG_MPC860SAR
412#define BCSR4_UTOPIA_EN ((uint)0x08000000)
413#endif /* CONFIG_MPC860SAR */
414#ifdef CONFIG_MPC860T
415#define BCSR4_FETH_EN ((uint)0x08000000)
416#endif /* CONFIG_MPC860T */
417#ifdef CONFIG_MPC823
418#define BCSR4_USB_SPEED ((uint)0x04000000)
419#endif /* CONFIG_MPC823 */
420#ifdef CONFIG_MPC860T
421#define BCSR4_FETHCFG0 ((uint)0x04000000)
422#endif /* CONFIG_MPC860T */
423#ifdef CONFIG_MPC823
424#define BCSR4_VCCO ((uint)0x02000000)
425#endif /* CONFIG_MPC823 */
426#ifdef CONFIG_MPC860T
427#define BCSR4_FETHFDE ((uint)0x02000000)
428#endif /* CONFIG_MPC860T */
429#ifdef CONFIG_MPC823
430#define BCSR4_VIDEO_ON ((uint)0x00800000)
431#endif /* CONFIG_MPC823 */
432#ifdef CONFIG_MPC823
433#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
434#endif /* CONFIG_MPC823 */
435#ifdef CONFIG_MPC860T
436#define BCSR4_FETHCFG1 ((uint)0x00400000)
437#endif /* CONFIG_MPC860T */
438#ifdef CONFIG_MPC823
439#define BCSR4_VIDEO_RST ((uint)0x00200000)
440#endif /* CONFIG_MPC823 */
441#ifdef CONFIG_MPC860T
442#define BCSR4_FETHRST ((uint)0x00200000)
443#endif /* CONFIG_MPC860T */
444#ifdef CONFIG_MPC823
445#define BCSR4_MODEM_EN ((uint)0x00100000)
446#endif /* CONFIG_MPC823 */
447#ifdef CONFIG_MPC823
448#define BCSR4_DATA_VOICE ((uint)0x00080000)
449#endif /* CONFIG_MPC823 */
450#ifdef CONFIG_MPC850
451#define BCSR4_DATA_VOICE ((uint)0x00080000)
452#endif /* CONFIG_MPC850 */
453
454#define CONFIG_DRAM_50MHZ 1
455#define CONFIG_SDRAM_50MHZ
456
wdenk5b1d7132002-11-03 00:07:02 +0000457/* We don't use the 8259.
458*/
459#define NR_8259_INTS 0
460
wdenk5b1d7132002-11-03 00:07:02 +0000461/*
462 * MPC8xx CPM Options
463 */
464#define CONFIG_SCC_ENET 1
465#define CONFIG_SCC2_ENET 1
466#undef CONFIG_FEC_ENET
467#undef CONFIG_CPM_IIC
468#undef CONFIG_UCODE_PATCH
469
470#define CONFIG_DISK_SPINUP_TIME 1000000
471
472/* PCMCIA configuration */
473
474#define PCMCIA_MAX_SLOTS 1
475
476#ifdef CONFIG_MPC860
477#define PCMCIA_SLOT_A 1
478#endif
479
wdenk180d3f72004-01-04 16:28:35 +0000480#define CFG_DAUGHTERBOARD
481
wdenk5b1d7132002-11-03 00:07:02 +0000482#endif /* __CONFIG_H */