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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * Basic I2C functions
3 *
4 * Copyright (c) 2004 Texas Instruments
5 *
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15 *
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
18 *
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20 *
Lubomir Popov960187f2013-06-01 06:44:38 +000021 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24 * OMAPs and derivatives as well. The only anticipated exception would
25 * be the OMAP2420, which shall require driver modification.
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
30 * hang the system under certain conditions (e.g. unconfigured pads).
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
33 * (except for OMAP243X and OMAP34XX).
34 * - Driver now supports up to I2C5 (OMAP5).
Hannes Petermaierd5243352014-02-03 21:22:18 +010035 *
Hannes Schmelzer4c302b92015-05-28 15:41:12 +020036 * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
Hannes Petermaierd5243352014-02-03 21:22:18 +010037 * - Added support for set_speed
38 *
wdenk8ed96042005-01-09 23:16:25 +000039 */
40
41#include <common.h>
Mugunthan V Ndaa69ff2016-07-18 15:11:01 +053042#include <dm.h>
Heiko Schocher6789e842013-10-22 11:03:18 +020043#include <i2c.h>
wdenk289f9322005-01-12 00:15:14 +000044
wdenk8ed96042005-01-09 23:16:25 +000045#include <asm/arch/i2c.h>
46#include <asm/io.h>
47
Steve Sakoman938717c2010-06-12 06:42:57 -070048#include "omap24xx_i2c.h"
49
Tom Rinicec487a2012-02-20 18:49:16 +000050#define I2C_TIMEOUT 1000
Steve Sakomand7083952010-07-19 20:31:55 -070051
Lubomir Popov960187f2013-06-01 06:44:38 +000052/* Absolutely safe for status update at 100 kHz I2C: */
53#define I2C_WAIT 200
54
Mugunthan V Ndaa69ff2016-07-18 15:11:01 +053055struct omap_i2c {
56 struct udevice *clk;
57 struct i2c *regs;
58 unsigned int speed;
59 int waitdelay;
60 int clk_id;
61};
62
Hannes Petermaierd5243352014-02-03 21:22:18 +010063static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
64{
Lukasz Majewskib52a3fa2017-03-15 16:59:23 +010065 unsigned long internal_clk = 0, fclk;
66 unsigned int prescaler;
wdenk8ed96042005-01-09 23:16:25 +000067
Hannes Petermaierd5243352014-02-03 21:22:18 +010068 /*
Lukasz Majewskib52a3fa2017-03-15 16:59:23 +010069 * This method is only called for Standard and Fast Mode speeds
70 *
71 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
72 * page 5685, Table 24-7)
73 * that the internal I2C clock (after prescaler) should be between
74 * 7-12 MHz (at least for Fast Mode (FS)).
75 *
76 * Such approach is used in v4.9 Linux kernel in:
77 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
Hannes Petermaierd5243352014-02-03 21:22:18 +010078 */
Hannes Petermaierd5243352014-02-03 21:22:18 +010079
Lukasz Majewskib52a3fa2017-03-15 16:59:23 +010080 speed /= 1000; /* convert speed to kHz */
Hannes Petermaierd5243352014-02-03 21:22:18 +010081
Lukasz Majewskib52a3fa2017-03-15 16:59:23 +010082 if (speed > 100)
83 internal_clk = 9600;
84 else
85 internal_clk = 4000;
Hannes Petermaierd5243352014-02-03 21:22:18 +010086
Lukasz Majewskib52a3fa2017-03-15 16:59:23 +010087 fclk = I2C_IP_CLK / 1000;
88 prescaler = fclk / internal_clk;
89 prescaler = prescaler - 1;
90
91 if (speed > 100) {
92 unsigned long scl;
93
94 /* Fast mode */
95 scl = internal_clk / speed;
96 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
97 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
98 } else {
99 /* Standard mode */
100 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
101 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
Hannes Petermaierd5243352014-02-03 21:22:18 +0100102 }
Lukasz Majewskib52a3fa2017-03-15 16:59:23 +0100103
104 debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
105 __func__, speed, prescaler, *pscl, *psch);
106
107 if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
108 return -EINVAL;
109
110 return prescaler;
Hannes Petermaierd5243352014-02-03 21:22:18 +0100111}
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530112
113/*
114 * Wait for the bus to be free by checking the Bus Busy (BB)
115 * bit to become clear
116 */
117static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
wdenk8ed96042005-01-09 23:16:25 +0000118{
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530119 int timeout = I2C_TIMEOUT;
120 u16 stat;
121
122 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
Tom Rini8f339d22017-05-12 22:33:15 -0400123#if defined(CONFIG_OMAP34XX)
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530124 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
125#else
126 /* Read RAW status */
127 while ((stat = readw(&i2c_base->irqstatus_raw) &
128 I2C_STAT_BB) && timeout--) {
129#endif
130 writew(stat, &i2c_base->stat);
131 udelay(waitdelay);
132 }
133
134 if (timeout <= 0) {
135 printf("Timed out in wait_for_bb: status=%04x\n",
136 stat);
137 return 1;
138 }
139 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
140 return 0;
141}
142
143/*
144 * Wait for the I2C controller to complete current action
145 * and update status
146 */
147static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
148{
149 u16 status;
150 int timeout = I2C_TIMEOUT;
151
152 do {
153 udelay(waitdelay);
Tom Rini8f339d22017-05-12 22:33:15 -0400154#if defined(CONFIG_OMAP34XX)
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530155 status = readw(&i2c_base->stat);
156#else
157 /* Read RAW status */
158 status = readw(&i2c_base->irqstatus_raw);
159#endif
160 } while (!(status &
161 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
162 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
163 I2C_STAT_AL)) && timeout--);
164
165 if (timeout <= 0) {
166 printf("Timed out in wait_for_event: status=%04x\n",
167 status);
168 /*
169 * If status is still 0 here, probably the bus pads have
170 * not been configured for I2C, and/or pull-ups are missing.
171 */
172 printf("Check if pads/pull-ups of bus are properly configured\n");
173 writew(0xFFFF, &i2c_base->stat);
174 status = 0;
175 }
176
177 return status;
178}
179
180static void flush_fifo(struct i2c *i2c_base)
181{
182 u16 stat;
183
184 /*
185 * note: if you try and read data when its not there or ready
186 * you get a bus error
187 */
188 while (1) {
189 stat = readw(&i2c_base->stat);
190 if (stat == I2C_STAT_RRDY) {
191 readb(&i2c_base->data);
192 writew(I2C_STAT_RRDY, &i2c_base->stat);
193 udelay(1000);
194 } else
195 break;
196 }
197}
198
199static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
200 int *waitdelay)
201{
Hannes Petermaierd5243352014-02-03 21:22:18 +0100202 int psc, fsscll = 0, fssclh = 0;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500203 int hsscll = 0, hssclh = 0;
Hannes Petermaierd5243352014-02-03 21:22:18 +0100204 u32 scll = 0, sclh = 0;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500205
Hannes Petermaierd5243352014-02-03 21:22:18 +0100206 if (speed >= OMAP_I2C_HIGH_SPEED) {
Tom Rix7f79dfb2009-06-28 12:52:27 -0500207 /* High speed */
Hannes Petermaierd5243352014-02-03 21:22:18 +0100208 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
209 psc -= 1;
210 if (psc < I2C_PSC_MIN) {
211 printf("Error : I2C unsupported prescaler %d\n", psc);
212 return -1;
213 }
Tom Rix7f79dfb2009-06-28 12:52:27 -0500214
215 /* For first phase of HS mode */
Hannes Petermaierd5243352014-02-03 21:22:18 +0100216 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
217
218 fssclh = fsscll;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500219
220 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
221 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
222 if (((fsscll < 0) || (fssclh < 0)) ||
223 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000224 puts("Error : I2C initializing first phase clock\n");
Hannes Petermaierd5243352014-02-03 21:22:18 +0100225 return -1;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500226 }
227
228 /* For second phase of HS mode */
229 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
230
231 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
232 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
233 if (((fsscll < 0) || (fssclh < 0)) ||
234 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000235 puts("Error : I2C initializing second phase clock\n");
Hannes Petermaierd5243352014-02-03 21:22:18 +0100236 return -1;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500237 }
238
239 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
240 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
241
242 } else {
243 /* Standard and fast speed */
Hannes Petermaierd5243352014-02-03 21:22:18 +0100244 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
245 if (0 > psc) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000246 puts("Error : I2C initializing clock\n");
Hannes Petermaierd5243352014-02-03 21:22:18 +0100247 return -1;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500248 }
Tom Rix7f79dfb2009-06-28 12:52:27 -0500249 }
wdenk8ed96042005-01-09 23:16:25 +0000250
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530251 *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
Hannes Petermaierd5243352014-02-03 21:22:18 +0100252 writew(0, &i2c_base->con);
253 writew(psc, &i2c_base->psc);
254 writew(scll, &i2c_base->scll);
255 writew(sclh, &i2c_base->sclh);
256 writew(I2C_CON_EN, &i2c_base->con);
257 writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
258
259 return 0;
260}
Heiko Schocherf7c10532014-06-30 09:12:09 +0200261
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530262static void omap24_i2c_deblock(struct i2c *i2c_base)
Heiko Schocherf7c10532014-06-30 09:12:09 +0200263{
Heiko Schocherf7c10532014-06-30 09:12:09 +0200264 int i;
265 u16 systest;
266 u16 orgsystest;
267
268 /* set test mode ST_EN = 1 */
269 orgsystest = readw(&i2c_base->systest);
270 systest = orgsystest;
271 /* enable testmode */
272 systest |= I2C_SYSTEST_ST_EN;
273 writew(systest, &i2c_base->systest);
274 systest &= ~I2C_SYSTEST_TMODE_MASK;
275 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
276 writew(systest, &i2c_base->systest);
277
278 /* set SCL, SDA = 1 */
279 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
280 writew(systest, &i2c_base->systest);
281 udelay(10);
282
283 /* toggle scl 9 clocks */
284 for (i = 0; i < 9; i++) {
285 /* SCL = 0 */
286 systest &= ~I2C_SYSTEST_SCL_O;
287 writew(systest, &i2c_base->systest);
288 udelay(10);
289 /* SCL = 1 */
290 systest |= I2C_SYSTEST_SCL_O;
291 writew(systest, &i2c_base->systest);
292 udelay(10);
293 }
294
295 /* send stop */
296 systest &= ~I2C_SYSTEST_SDA_O;
297 writew(systest, &i2c_base->systest);
298 udelay(10);
299 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
300 writew(systest, &i2c_base->systest);
301 udelay(10);
302
303 /* restore original mode */
304 writew(orgsystest, &i2c_base->systest);
305}
306
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530307static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
308 int *waitdelay)
Hannes Petermaierd5243352014-02-03 21:22:18 +0100309{
Hannes Petermaierd5243352014-02-03 21:22:18 +0100310 int timeout = I2C_TIMEOUT;
Heiko Schocherf7c10532014-06-30 09:12:09 +0200311 int deblock = 1;
Hannes Petermaierd5243352014-02-03 21:22:18 +0100312
Heiko Schocherf7c10532014-06-30 09:12:09 +0200313retry:
Michael Jones89677b22011-07-27 14:01:55 -0400314 if (readw(&i2c_base->con) & I2C_CON_EN) {
315 writew(0, &i2c_base->con);
316 udelay(50000);
wdenk8ed96042005-01-09 23:16:25 +0000317 }
318
Tom Rinicec487a2012-02-20 18:49:16 +0000319 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
320 udelay(1000);
321
322 writew(I2C_CON_EN, &i2c_base->con);
323 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
324 if (timeout <= 0) {
325 puts("ERROR: Timeout in soft-reset\n");
326 return;
327 }
328 udelay(1000);
329 }
330
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530331 if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
Hannes Petermaierd5243352014-02-03 21:22:18 +0100332 printf("ERROR: failed to setup I2C bus-speed!\n");
333 return;
334 }
Tom Rix7f79dfb2009-06-28 12:52:27 -0500335
wdenk8ed96042005-01-09 23:16:25 +0000336 /* own address */
Michael Jones89677b22011-07-27 14:01:55 -0400337 writew(slaveadd, &i2c_base->oa);
Hannes Petermaierd5243352014-02-03 21:22:18 +0100338
Tom Rini8f339d22017-05-12 22:33:15 -0400339#if defined(CONFIG_OMAP34XX)
Lubomir Popov960187f2013-06-01 06:44:38 +0000340 /*
341 * Have to enable interrupts for OMAP2/3, these IPs don't have
342 * an 'irqstatus_raw' register and we shall have to poll 'stat'
343 */
Michael Jones89677b22011-07-27 14:01:55 -0400344 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
Lubomir Popov960187f2013-06-01 06:44:38 +0000345 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
346#endif
Michael Jones89677b22011-07-27 14:01:55 -0400347 udelay(1000);
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530348 flush_fifo(i2c_base);
Michael Jones89677b22011-07-27 14:01:55 -0400349 writew(0xFFFF, &i2c_base->stat);
Heiko Schocherf7c10532014-06-30 09:12:09 +0200350
351 /* Handle possible failed I2C state */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530352 if (wait_for_bb(i2c_base, *waitdelay))
Heiko Schocherf7c10532014-06-30 09:12:09 +0200353 if (deblock == 1) {
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530354 omap24_i2c_deblock(i2c_base);
Heiko Schocherf7c10532014-06-30 09:12:09 +0200355 deblock = 0;
356 goto retry;
357 }
Tom Rinicec487a2012-02-20 18:49:16 +0000358}
359
Lubomir Popov960187f2013-06-01 06:44:38 +0000360/*
361 * i2c_probe: Use write access. Allows to identify addresses that are
362 * write-only (like the config register of dual-port EEPROMs)
363 */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530364static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
wdenk8ed96042005-01-09 23:16:25 +0000365{
Tom Rinicec487a2012-02-20 18:49:16 +0000366 u16 status;
wdenk8ed96042005-01-09 23:16:25 +0000367 int res = 1; /* default = fail */
368
Michael Jones89677b22011-07-27 14:01:55 -0400369 if (chip == readw(&i2c_base->oa))
wdenk8ed96042005-01-09 23:16:25 +0000370 return res;
wdenk8ed96042005-01-09 23:16:25 +0000371
Lubomir Popov960187f2013-06-01 06:44:38 +0000372 /* Wait until bus is free */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530373 if (wait_for_bb(i2c_base, waitdelay))
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000374 return res;
wdenk8ed96042005-01-09 23:16:25 +0000375
Lubomir Popov960187f2013-06-01 06:44:38 +0000376 /* No data transfer, slave addr only */
Michael Jones89677b22011-07-27 14:01:55 -0400377 writew(chip, &i2c_base->sa);
Lubomir Popov960187f2013-06-01 06:44:38 +0000378 /* Stop bit needed here */
379 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
380 I2C_CON_STP, &i2c_base->con);
wdenk8ed96042005-01-09 23:16:25 +0000381
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530382 status = wait_for_event(i2c_base, waitdelay);
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000383
Lubomir Popov960187f2013-06-01 06:44:38 +0000384 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
385 /*
386 * With current high-level command implementation, notifying
387 * the user shall flood the console with 127 messages. If
388 * silent exit is desired upon unconfigured bus, remove the
389 * following 'if' section:
390 */
391 if (status == I2C_STAT_XRDY)
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530392 printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
393 status);
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000394
Lubomir Popov960187f2013-06-01 06:44:38 +0000395 goto pr_exit;
Tom Rini168a5ac2012-05-21 06:46:29 +0000396 }
Tom Rinicec487a2012-02-20 18:49:16 +0000397
Lubomir Popov960187f2013-06-01 06:44:38 +0000398 /* Check for ACK (!NAK) */
399 if (!(status & I2C_STAT_NACK)) {
Hannes Petermaierd5243352014-02-03 21:22:18 +0100400 res = 0; /* Device found */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530401 udelay(waitdelay);/* Required by AM335X in SPL */
Lubomir Popov960187f2013-06-01 06:44:38 +0000402 /* Abort transfer (force idle state) */
403 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
404 udelay(1000);
405 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
406 I2C_CON_STP, &i2c_base->con); /* STP */
407 }
408pr_exit:
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530409 flush_fifo(i2c_base);
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100410 writew(0xFFFF, &i2c_base->stat);
wdenk8ed96042005-01-09 23:16:25 +0000411 return res;
412}
413
Lubomir Popov960187f2013-06-01 06:44:38 +0000414/*
415 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
416 * of the requested number of bytes (note that the 'i2c md' command
417 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
418 * defined in the board config header, this transaction shall be with
419 * Repeated Start (Sr) between the address and data phases; otherwise
420 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
421 * The address (reg offset) may be 0, 1 or 2 bytes long.
422 * Function now reads correctly from chips that return more than one
423 * byte of data per addressed register (like TI temperature sensors),
424 * or that do not need a register address at all (such as some clock
425 * distributors).
426 */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530427static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
428 uint addr, int alen, uchar *buffer, int len)
wdenk8ed96042005-01-09 23:16:25 +0000429{
Lubomir Popov960187f2013-06-01 06:44:38 +0000430 int i2c_error = 0;
431 u16 status;
432
433 if (alen < 0) {
434 puts("I2C read: addr len < 0\n");
435 return 1;
436 }
437 if (len < 0) {
438 puts("I2C read: data len < 0\n");
439 return 1;
440 }
441 if (buffer == NULL) {
442 puts("I2C read: NULL pointer passed\n");
443 return 1;
444 }
wdenk8ed96042005-01-09 23:16:25 +0000445
Ilya Yanok55faa582012-06-08 03:12:09 +0000446 if (alen > 2) {
Tom Rinicec487a2012-02-20 18:49:16 +0000447 printf("I2C read: addr len %d not supported\n", alen);
wdenk8ed96042005-01-09 23:16:25 +0000448 return 1;
Tom Rinicec487a2012-02-20 18:49:16 +0000449 }
wdenk8ed96042005-01-09 23:16:25 +0000450
Ilya Yanok55faa582012-06-08 03:12:09 +0000451 if (addr + len > (1 << 16)) {
Tom Rinicec487a2012-02-20 18:49:16 +0000452 puts("I2C read: address out of range\n");
453 return 1;
454 }
455
Guy Thouret32b9b552016-03-11 16:23:41 +0000456#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
457 /*
458 * EEPROM chips that implement "address overflow" are ones
459 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
460 * address and the extra bits end up in the "chip address"
461 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
462 * four 256 byte chips.
463 *
464 * Note that we consider the length of the address field to
465 * still be one byte because the extra address bits are
466 * hidden in the chip address.
467 */
468 if (alen > 0)
469 chip |= ((addr >> (alen * 8)) &
470 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
471#endif
472
Lubomir Popov960187f2013-06-01 06:44:38 +0000473 /* Wait until bus not busy */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530474 if (wait_for_bb(i2c_base, waitdelay))
Lubomir Popov960187f2013-06-01 06:44:38 +0000475 return 1;
476
477 /* Zero, one or two bytes reg address (offset) */
478 writew(alen, &i2c_base->cnt);
479 /* Set slave address */
480 writew(chip, &i2c_base->sa);
481
482 if (alen) {
483 /* Must write reg offset first */
484#ifdef CONFIG_I2C_REPEATED_START
485 /* No stop bit, use Repeated Start (Sr) */
486 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
487 I2C_CON_TRX, &i2c_base->con);
488#else
489 /* Stop - Start (P-S) */
490 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
491 I2C_CON_TRX, &i2c_base->con);
492#endif
493 /* Send register offset */
494 while (1) {
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530495 status = wait_for_event(i2c_base, waitdelay);
Lubomir Popov960187f2013-06-01 06:44:38 +0000496 /* Try to identify bus that is not padconf'd for I2C */
497 if (status == I2C_STAT_XRDY) {
498 i2c_error = 2;
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530499 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
500 status);
Lubomir Popov960187f2013-06-01 06:44:38 +0000501 goto rd_exit;
502 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100503 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000504 i2c_error = 1;
505 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
506 status);
507 goto rd_exit;
508 }
509 if (alen) {
510 if (status & I2C_STAT_XRDY) {
511 alen--;
512 /* Do we have to use byte access? */
513 writeb((addr >> (8 * alen)) & 0xff,
514 &i2c_base->data);
515 writew(I2C_STAT_XRDY, &i2c_base->stat);
516 }
517 }
518 if (status & I2C_STAT_ARDY) {
519 writew(I2C_STAT_ARDY, &i2c_base->stat);
520 break;
521 }
522 }
523 }
524 /* Set slave address */
525 writew(chip, &i2c_base->sa);
526 /* Read len bytes from slave */
527 writew(len, &i2c_base->cnt);
528 /* Need stop bit here */
529 writew(I2C_CON_EN | I2C_CON_MST |
530 I2C_CON_STT | I2C_CON_STP,
531 &i2c_base->con);
532
533 /* Receive data */
534 while (1) {
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530535 status = wait_for_event(i2c_base, waitdelay);
Lubomir Popov960187f2013-06-01 06:44:38 +0000536 /*
537 * Try to identify bus that is not padconf'd for I2C. This
538 * state could be left over from previous transactions if
539 * the address phase is skipped due to alen=0.
540 */
541 if (status == I2C_STAT_XRDY) {
542 i2c_error = 2;
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530543 printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
544 status);
Lubomir Popov960187f2013-06-01 06:44:38 +0000545 goto rd_exit;
546 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100547 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000548 i2c_error = 1;
549 goto rd_exit;
550 }
551 if (status & I2C_STAT_RRDY) {
552 *buffer++ = readb(&i2c_base->data);
553 writew(I2C_STAT_RRDY, &i2c_base->stat);
554 }
555 if (status & I2C_STAT_ARDY) {
556 writew(I2C_STAT_ARDY, &i2c_base->stat);
557 break;
wdenk8ed96042005-01-09 23:16:25 +0000558 }
559 }
560
Lubomir Popov960187f2013-06-01 06:44:38 +0000561rd_exit:
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530562 flush_fifo(i2c_base);
Lubomir Popov960187f2013-06-01 06:44:38 +0000563 writew(0xFFFF, &i2c_base->stat);
Lubomir Popov960187f2013-06-01 06:44:38 +0000564 return i2c_error;
wdenk8ed96042005-01-09 23:16:25 +0000565}
566
Lubomir Popov960187f2013-06-01 06:44:38 +0000567/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530568static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
569 uint addr, int alen, uchar *buffer, int len)
wdenk8ed96042005-01-09 23:16:25 +0000570{
Tom Rinicec487a2012-02-20 18:49:16 +0000571 int i;
572 u16 status;
573 int i2c_error = 0;
Hannes Petermaierd5243352014-02-03 21:22:18 +0100574 int timeout = I2C_TIMEOUT;
Lubomir Popov960187f2013-06-01 06:44:38 +0000575
576 if (alen < 0) {
577 puts("I2C write: addr len < 0\n");
578 return 1;
579 }
580
581 if (len < 0) {
582 puts("I2C write: data len < 0\n");
583 return 1;
584 }
585
586 if (buffer == NULL) {
587 puts("I2C write: NULL pointer passed\n");
588 return 1;
589 }
wdenk8ed96042005-01-09 23:16:25 +0000590
Ilya Yanok55faa582012-06-08 03:12:09 +0000591 if (alen > 2) {
Tom Rinicec487a2012-02-20 18:49:16 +0000592 printf("I2C write: addr len %d not supported\n", alen);
wdenk8ed96042005-01-09 23:16:25 +0000593 return 1;
Tom Rinicec487a2012-02-20 18:49:16 +0000594 }
wdenk8ed96042005-01-09 23:16:25 +0000595
Ilya Yanok55faa582012-06-08 03:12:09 +0000596 if (addr + len > (1 << 16)) {
Tom Rinicec487a2012-02-20 18:49:16 +0000597 printf("I2C write: address 0x%x + 0x%x out of range\n",
Lubomir Popov960187f2013-06-01 06:44:38 +0000598 addr, len);
wdenk8ed96042005-01-09 23:16:25 +0000599 return 1;
600 }
601
Guy Thouret32b9b552016-03-11 16:23:41 +0000602#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
603 /*
604 * EEPROM chips that implement "address overflow" are ones
605 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
606 * address and the extra bits end up in the "chip address"
607 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
608 * four 256 byte chips.
609 *
610 * Note that we consider the length of the address field to
611 * still be one byte because the extra address bits are
612 * hidden in the chip address.
613 */
614 if (alen > 0)
615 chip |= ((addr >> (alen * 8)) &
616 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
617#endif
618
Lubomir Popov960187f2013-06-01 06:44:38 +0000619 /* Wait until bus not busy */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530620 if (wait_for_bb(i2c_base, waitdelay))
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000621 return 1;
Michael Jones0607e2b2011-09-04 14:01:55 -0400622
Lubomir Popov960187f2013-06-01 06:44:38 +0000623 /* Start address phase - will write regoffset + len bytes data */
Tom Rinicec487a2012-02-20 18:49:16 +0000624 writew(alen + len, &i2c_base->cnt);
Lubomir Popov960187f2013-06-01 06:44:38 +0000625 /* Set slave address */
Michael Jones0607e2b2011-09-04 14:01:55 -0400626 writew(chip, &i2c_base->sa);
Lubomir Popov960187f2013-06-01 06:44:38 +0000627 /* Stop bit needed here */
Michael Jones0607e2b2011-09-04 14:01:55 -0400628 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
Lubomir Popov960187f2013-06-01 06:44:38 +0000629 I2C_CON_STP, &i2c_base->con);
Michael Jones0607e2b2011-09-04 14:01:55 -0400630
Lubomir Popov960187f2013-06-01 06:44:38 +0000631 while (alen) {
632 /* Must write reg offset (one or two bytes) */
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530633 status = wait_for_event(i2c_base, waitdelay);
Lubomir Popov960187f2013-06-01 06:44:38 +0000634 /* Try to identify bus that is not padconf'd for I2C */
635 if (status == I2C_STAT_XRDY) {
636 i2c_error = 2;
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530637 printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
638 status);
Lubomir Popov960187f2013-06-01 06:44:38 +0000639 goto wr_exit;
640 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100641 if (status == 0 || (status & I2C_STAT_NACK)) {
Michael Jones0607e2b2011-09-04 14:01:55 -0400642 i2c_error = 1;
Lubomir Popov960187f2013-06-01 06:44:38 +0000643 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
644 status);
645 goto wr_exit;
Tom Rinicec487a2012-02-20 18:49:16 +0000646 }
Tom Rinicec487a2012-02-20 18:49:16 +0000647 if (status & I2C_STAT_XRDY) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000648 alen--;
649 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
Tom Rinicec487a2012-02-20 18:49:16 +0000650 writew(I2C_STAT_XRDY, &i2c_base->stat);
651 } else {
652 i2c_error = 1;
Lubomir Popov960187f2013-06-01 06:44:38 +0000653 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
654 status);
655 goto wr_exit;
656 }
657 }
658 /* Address phase is over, now write data */
659 for (i = 0; i < len; i++) {
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530660 status = wait_for_event(i2c_base, waitdelay);
Hannes Petermaierd5243352014-02-03 21:22:18 +0100661 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000662 i2c_error = 1;
663 printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
664 status);
665 goto wr_exit;
666 }
667 if (status & I2C_STAT_XRDY) {
668 writeb(buffer[i], &i2c_base->data);
669 writew(I2C_STAT_XRDY, &i2c_base->stat);
670 } else {
671 i2c_error = 1;
672 printf("i2c_write: bus not ready for data Tx (i=%d)\n",
673 i);
674 goto wr_exit;
wdenk8ed96042005-01-09 23:16:25 +0000675 }
676 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100677 /*
678 * poll ARDY bit for making sure that last byte really has been
679 * transferred on the bus.
680 */
681 do {
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530682 status = wait_for_event(i2c_base, waitdelay);
Hannes Petermaierd5243352014-02-03 21:22:18 +0100683 } while (!(status & I2C_STAT_ARDY) && timeout--);
684 if (timeout <= 0)
685 printf("i2c_write: timed out writig last byte!\n");
wdenk8ed96042005-01-09 23:16:25 +0000686
Lubomir Popov960187f2013-06-01 06:44:38 +0000687wr_exit:
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530688 flush_fifo(i2c_base);
Michael Jones0607e2b2011-09-04 14:01:55 -0400689 writew(0xFFFF, &i2c_base->stat);
Tom Rinicec487a2012-02-20 18:49:16 +0000690 return i2c_error;
wdenk8ed96042005-01-09 23:16:25 +0000691}
692
Mugunthan V Ndaa69ff2016-07-18 15:11:01 +0530693#ifndef CONFIG_DM_I2C
Lubomir Popov960187f2013-06-01 06:44:38 +0000694/*
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530695 * The legacy I2C functions. These need to get removed once
696 * all users of this driver are converted to DM.
Lubomir Popov960187f2013-06-01 06:44:38 +0000697 */
Heiko Schocher6789e842013-10-22 11:03:18 +0200698static struct i2c *omap24_get_base(struct i2c_adapter *adap)
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100699{
Heiko Schocher6789e842013-10-22 11:03:18 +0200700 switch (adap->hwadapnr) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000701 case 0:
Heiko Schocher6789e842013-10-22 11:03:18 +0200702 return (struct i2c *)I2C_BASE1;
Lubomir Popov960187f2013-06-01 06:44:38 +0000703 break;
704 case 1:
Heiko Schocher6789e842013-10-22 11:03:18 +0200705 return (struct i2c *)I2C_BASE2;
Lubomir Popov960187f2013-06-01 06:44:38 +0000706 break;
Adam Fordac1d8ac2017-08-11 06:39:13 -0500707#if (CONFIG_SYS_I2C_BUS_MAX > 2)
Lubomir Popov960187f2013-06-01 06:44:38 +0000708 case 2:
Heiko Schocher6789e842013-10-22 11:03:18 +0200709 return (struct i2c *)I2C_BASE3;
Lubomir Popov960187f2013-06-01 06:44:38 +0000710 break;
Adam Fordac1d8ac2017-08-11 06:39:13 -0500711#if (CONFIG_SYS_I2C_BUS_MAX > 3)
Lubomir Popov960187f2013-06-01 06:44:38 +0000712 case 3:
Heiko Schocher6789e842013-10-22 11:03:18 +0200713 return (struct i2c *)I2C_BASE4;
Lubomir Popov960187f2013-06-01 06:44:38 +0000714 break;
Adam Fordac1d8ac2017-08-11 06:39:13 -0500715#if (CONFIG_SYS_I2C_BUS_MAX > 4)
Lubomir Popov960187f2013-06-01 06:44:38 +0000716 case 4:
Heiko Schocher6789e842013-10-22 11:03:18 +0200717 return (struct i2c *)I2C_BASE5;
Lubomir Popov960187f2013-06-01 06:44:38 +0000718 break;
719#endif
720#endif
721#endif
Heiko Schocher6789e842013-10-22 11:03:18 +0200722 default:
723 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
724 break;
Lubomir Popov960187f2013-06-01 06:44:38 +0000725 }
Heiko Schocher6789e842013-10-22 11:03:18 +0200726 return NULL;
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100727}
Steve Sakoman938717c2010-06-12 06:42:57 -0700728
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530729
730static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
731 int alen, uchar *buffer, int len)
732{
733 struct i2c *i2c_base = omap24_get_base(adap);
734
735 return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
736 alen, buffer, len);
737}
738
739
740static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
741 int alen, uchar *buffer, int len)
742{
743 struct i2c *i2c_base = omap24_get_base(adap);
744
745 return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
746 alen, buffer, len);
747}
748
749static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
750{
751 struct i2c *i2c_base = omap24_get_base(adap);
752 int ret;
753
754 ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
755 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900756 pr_err("%s: set i2c speed failed\n", __func__);
Mugunthan V Nbe243e42016-07-18 15:11:00 +0530757 return ret;
758 }
759
760 adap->speed = speed;
761
762 return 0;
763}
764
765static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
766{
767 struct i2c *i2c_base = omap24_get_base(adap);
768
769 return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
770}
771
772static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
773{
774 struct i2c *i2c_base = omap24_get_base(adap);
775
776 return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
777}
778
Heiko Schocher6789e842013-10-22 11:03:18 +0200779#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
780#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
781#endif
782#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
783#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
784#endif
785
786U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5243352014-02-03 21:22:18 +0100787 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Heiko Schocher6789e842013-10-22 11:03:18 +0200788 CONFIG_SYS_OMAP24_I2C_SPEED,
789 CONFIG_SYS_OMAP24_I2C_SLAVE,
790 0)
791U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5243352014-02-03 21:22:18 +0100792 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Heiko Schocher6789e842013-10-22 11:03:18 +0200793 CONFIG_SYS_OMAP24_I2C_SPEED1,
794 CONFIG_SYS_OMAP24_I2C_SLAVE1,
795 1)
Adam Fordac1d8ac2017-08-11 06:39:13 -0500796#if (CONFIG_SYS_I2C_BUS_MAX > 2)
Heiko Schocher6789e842013-10-22 11:03:18 +0200797#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
798#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
799#endif
800#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
801#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
802#endif
803
804U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
805 omap24_i2c_read, omap24_i2c_write, NULL,
806 CONFIG_SYS_OMAP24_I2C_SPEED2,
807 CONFIG_SYS_OMAP24_I2C_SLAVE2,
808 2)
Adam Fordac1d8ac2017-08-11 06:39:13 -0500809#if (CONFIG_SYS_I2C_BUS_MAX > 3)
Heiko Schocher6789e842013-10-22 11:03:18 +0200810#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
811#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
812#endif
813#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
814#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
815#endif
816
817U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
818 omap24_i2c_read, omap24_i2c_write, NULL,
819 CONFIG_SYS_OMAP24_I2C_SPEED3,
820 CONFIG_SYS_OMAP24_I2C_SLAVE3,
821 3)
Adam Fordac1d8ac2017-08-11 06:39:13 -0500822#if (CONFIG_SYS_I2C_BUS_MAX > 4)
Heiko Schocher6789e842013-10-22 11:03:18 +0200823#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
824#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
825#endif
826#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
827#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
828#endif
829
830U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
831 omap24_i2c_read, omap24_i2c_write, NULL,
832 CONFIG_SYS_OMAP24_I2C_SPEED4,
833 CONFIG_SYS_OMAP24_I2C_SLAVE4,
834 4)
835#endif
836#endif
837#endif
Mugunthan V Ndaa69ff2016-07-18 15:11:01 +0530838
839#else /* CONFIG_DM_I2C */
840
841static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
842{
843 struct omap_i2c *priv = dev_get_priv(bus);
844 int ret;
845
846 debug("i2c_xfer: %d messages\n", nmsgs);
847 for (; nmsgs > 0; nmsgs--, msg++) {
848 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
849 if (msg->flags & I2C_M_RD) {
850 ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
851 msg->addr, 0, 0, msg->buf,
852 msg->len);
853 } else {
854 ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
855 msg->addr, 0, 0, msg->buf,
856 msg->len);
857 }
858 if (ret) {
859 debug("i2c_write: error sending\n");
860 return -EREMOTEIO;
861 }
862 }
863
864 return 0;
865}
866
867static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
868{
869 struct omap_i2c *priv = dev_get_priv(bus);
870
871 priv->speed = speed;
872
873 return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
874}
875
876static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
877 uint chip_flags)
878{
879 struct omap_i2c *priv = dev_get_priv(bus);
880
881 return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
882}
883
884static int omap_i2c_probe(struct udevice *bus)
885{
886 struct omap_i2c *priv = dev_get_priv(bus);
887
888 __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
889
890 return 0;
891}
892
893static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
894{
895 struct omap_i2c *priv = dev_get_priv(bus);
896
Simon Glassa821c4a2017-05-17 17:18:05 -0600897 priv->regs = map_physmem(devfdt_get_addr(bus), sizeof(void *),
Mugunthan V Ndaa69ff2016-07-18 15:11:01 +0530898 MAP_NOCACHE);
899 priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
900
901 return 0;
902}
903
904static const struct dm_i2c_ops omap_i2c_ops = {
905 .xfer = omap_i2c_xfer,
906 .probe_chip = omap_i2c_probe_chip,
907 .set_bus_speed = omap_i2c_set_bus_speed,
908};
909
910static const struct udevice_id omap_i2c_ids[] = {
Adam Ford0fc8a3a2017-04-17 08:09:40 -0500911 { .compatible = "ti,omap3-i2c" },
Mugunthan V Ndaa69ff2016-07-18 15:11:01 +0530912 { .compatible = "ti,omap4-i2c" },
913 { }
914};
915
916U_BOOT_DRIVER(i2c_omap) = {
917 .name = "i2c_omap",
918 .id = UCLASS_I2C,
919 .of_match = omap_i2c_ids,
920 .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
921 .probe = omap_i2c_probe,
922 .priv_auto_alloc_size = sizeof(struct omap_i2c),
923 .ops = &omap_i2c_ops,
924 .flags = DM_FLAG_PRE_RELOC,
925};
926
927#endif /* CONFIG_DM_I2C */