| Frieder Schrempf | e6f48aa | 2021-09-29 16:42:41 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
| 2 | /* |
| 3 | * Copyright (C) 2017 exceet electronics GmbH |
| 4 | * Copyright (C) 2018 Kontron Electronics GmbH |
| 5 | */ |
| 6 | |
| 7 | #if defined(CONFIG_FIT) |
| 8 | |
| 9 | / { |
| 10 | binman: binman { |
| 11 | filename = "flash.bin"; |
| 12 | pad-byte = <0x00>; |
| 13 | |
| 14 | spl: blob-ext@1 { |
| 15 | offset = <0x0>; |
| 16 | filename = "SPL"; |
| 17 | }; |
| 18 | |
| 19 | uboot: blob-ext@2 { |
| 20 | offset = <0x11000>; |
| 21 | filename = "u-boot.img"; |
| 22 | }; |
| 23 | }; |
| 24 | }; |
| 25 | |
| 26 | #endif /* CONFIG_FIT */ |
| 27 | |
| 28 | /* |
| 29 | * To make the PHYs work, we need to set the reset pin once. Afterwards |
| 30 | * in Linux we can't assign the shared reset GPIO to the PHYs, as this |
| 31 | * would cause Linux to reset both PHYs every time one of them gets |
| 32 | * reinitialized. |
| 33 | * |
| 34 | * Also we disable the second ethernet as it currently doesn't work with |
| 35 | * the devicetree setup in U-Boot. |
| 36 | */ |
| 37 | |
| 38 | &fec1 { |
| 39 | pinctrl-names = "default"; |
| 40 | pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; |
| 41 | phy-mode = "rmii"; |
| 42 | phy-handle = <ðphy1>; |
| 43 | phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; |
| 44 | status = "okay"; |
| 45 | |
| 46 | mdio { |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <0>; |
| 49 | |
| 50 | ethphy1: ethernet-phy@1 { |
| 51 | reg = <1>; |
| 52 | micrel,led-mode = <0>; |
| 53 | clocks = <&clks IMX6UL_CLK_ENET_REF>; |
| 54 | clock-names = "rmii-ref"; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
| 58 | |
| 59 | &fec2 { |
| 60 | status = "disabled"; |
| 61 | /delete-property/ phy-handle; |
| 62 | /delete-node/ mdio; |
| 63 | }; |