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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiew777d1ab2008-01-15 14:00:25 -06002/*
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
Angelo Durgehello05ffdc82019-11-15 23:54:19 +01008 *
9 * Conversion to DM
10 * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
TsiChungLiew777d1ab2008-01-15 14:00:25 -060011 */
12
13#include <common.h>
Simon Glass7b51b572019-08-01 09:46:52 -060014#include <env.h>
Simon Glassdb41d652019-12-28 10:45:07 -070015#include <hang.h>
TsiChungLiew777d1ab2008-01-15 14:00:25 -060016#include <malloc.h>
17#include <command.h>
18#include <config.h>
19#include <net.h>
20#include <miiphy.h>
Simon Glassc05ed002020-05-10 11:40:11 -060021#include <linux/delay.h>
Simon Glass68a6aa82019-11-14 12:57:31 -070022#include <linux/mii.h>
Angelo Durgehello05ffdc82019-11-15 23:54:19 +010023#include <asm/immap.h>
24#include <asm/fsl_mcdmafec.h>
25
26#include "MCD_dma.h"
TsiChungLiew777d1ab2008-01-15 14:00:25 -060027
TsiChungLiew777d1ab2008-01-15 14:00:25 -060028#undef ET_DEBUG
29#undef MII_DEBUG
30
31/* Ethernet Transmit and Receive Buffers */
32#define DBUF_LENGTH 1520
33#define PKT_MAXBUF_SIZE 1518
TsiChungLiew777d1ab2008-01-15 14:00:25 -060034#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
35
36/* RxBD bits definitions */
37#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
38 BD_ENET_RX_OV | BD_ENET_RX_TR)
39
Angelo Durgehello05ffdc82019-11-15 23:54:19 +010040DECLARE_GLOBAL_DATA_PTR;
TsiChungLiew777d1ab2008-01-15 14:00:25 -060041
Angelo Durgehello05ffdc82019-11-15 23:54:19 +010042static void init_eth_info(struct fec_info_dma *info)
43{
44 /* setup Receive and Transmit buffer descriptor */
45#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
46 static u32 tmp;
TsiChungLiew777d1ab2008-01-15 14:00:25 -060047
Angelo Durgehello05ffdc82019-11-15 23:54:19 +010048 if (info->index == 0)
49 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
50 else
51 info->rxbd = (cbd_t *)DBUF_LENGTH;
52
53 info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
54 tmp = (u32)info->rxbd;
55 info->txbd =
56 (cbd_t *)((u32)info->txbd + tmp +
57 (PKTBUFSRX * sizeof(cbd_t)));
58 tmp = (u32)info->txbd;
59 info->txbuf =
60 (char *)((u32)info->txbuf + tmp +
61 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
62 tmp = (u32)info->txbuf;
TsiChung Liewf32f7fe2008-04-30 12:11:19 -050063#else
Angelo Durgehello05ffdc82019-11-15 23:54:19 +010064 info->rxbd =
65 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
66 (PKTBUFSRX * sizeof(cbd_t)));
67 info->txbd =
68 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
69 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
70 info->txbuf =
71 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
TsiChung Liewf32f7fe2008-04-30 12:11:19 -050072#endif
TsiChungLiew777d1ab2008-01-15 14:00:25 -060073
Angelo Durgehello05ffdc82019-11-15 23:54:19 +010074#ifdef ET_DEBUG
75 printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
76#endif
77 info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
78}
79
80static void fec_halt(struct udevice *dev)
81{
82 struct fec_info_dma *info = dev->priv;
83 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
84 int counter = 0xffff;
85
86 /* issue graceful stop command to the FEC transmitter if necessary */
87 fecp->tcr |= FEC_TCR_GTS;
88
89 /* wait for graceful stop to register */
90 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
91 ;
92
93 /* Disable DMA tasks */
94 MCD_killDma(info->tx_task);
95 MCD_killDma(info->rx_task);
96
97 /* Disable the Ethernet Controller */
98 fecp->ecr &= ~FEC_ECR_ETHER_EN;
99
100 /* Clear FIFO status registers */
101 fecp->rfsr &= FIFO_ERRSTAT;
102 fecp->tfsr &= FIFO_ERRSTAT;
103
104 fecp->frst = 0x01000000;
105
106 /* Issue a reset command to the FEC chip */
107 fecp->ecr |= FEC_ECR_RESET;
108
109 /* wait at least 20 clock cycles */
110 mdelay(10);
111
112#ifdef ET_DEBUG
113 printf("Ethernet task stopped\n");
114#endif
115}
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600116
117#ifdef ET_DEBUG
118static void dbg_fec_regs(struct eth_device *dev)
119{
120 struct fec_info_dma *info = dev->priv;
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100121 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600122
123 printf("=====\n");
124 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
125 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
126 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
127 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
128 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
129 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
130 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
131 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
132 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
133 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
134 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
135 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
136 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
137 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
138 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
139 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
140 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
141 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
142 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
143 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
144 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
145 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
146 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
147 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
148 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
149 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
150 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
151 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
152 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
153 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
154 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
155 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
156 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
157 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
158 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
159}
160#endif
161
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100162static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600163{
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900164 struct bd_info *bd = gd->bd;
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100165
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600166 if ((dup_spd >> 16) == FULL) {
167 /* Set maximum frame length */
168 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
169 FEC_RCR_PROM | 0x100;
170 fecp->tcr = FEC_TCR_FDEN;
171 } else {
172 /* Half duplex mode */
173 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
174 FEC_RCR_MII_MODE | FEC_RCR_DRT;
175 fecp->tcr &= ~FEC_TCR_FDEN;
176 }
177
178 if ((dup_spd & 0xFFFF) == _100BASET) {
179#ifdef MII_DEBUG
180 printf("100Mbps\n");
181#endif
182 bd->bi_ethspeed = 100;
183 } else {
184#ifdef MII_DEBUG
185 printf("10Mbps\n");
186#endif
187 bd->bi_ethspeed = 10;
188 }
189}
190
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100191static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600192{
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100193 u8 curr_byte; /* byte for which to compute the CRC */
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600194 int byte; /* loop - counter */
195 int bit; /* loop - counter */
196 u32 crc = 0xffffffff; /* initial value */
197
198 for (byte = 0; byte < 6; byte++) {
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100199 curr_byte = mac[byte];
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600200 for (bit = 0; bit < 8; bit++) {
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100201 if ((curr_byte & 0x01) ^ (crc & 0x01)) {
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600202 crc >>= 1;
203 crc = crc ^ 0xedb88320;
204 } else {
205 crc >>= 1;
206 }
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100207 curr_byte >>= 1;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600208 }
209 }
210
211 crc = crc >> 26;
212
213 /* Set individual hash table register */
214 if (crc >= 32) {
215 fecp->ialr = (1 << (crc - 32));
216 fecp->iaur = 0;
217 } else {
218 fecp->ialr = 0;
219 fecp->iaur = (1 << crc);
220 }
221
222 /* Set physical address */
223 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
224 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
225
226 /* Clear multicast address hash table */
227 fecp->gaur = 0;
228 fecp->galr = 0;
229}
230
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100231static int fec_init(struct udevice *dev)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600232{
233 struct fec_info_dma *info = dev->priv;
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100234 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
235 int rval, i;
Mike Frysingerd3f87142009-02-11 19:01:26 -0500236 uchar enetaddr[6];
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600237
238#ifdef ET_DEBUG
239 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
240#endif
241
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100242 fecpin_setclear(info, 1);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600243 fec_halt(dev);
244
245#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 defined (CONFIG_SYS_DISCOVER_PHY)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600247
248 mii_init();
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100249 set_fec_duplex_speed(fecp, info->dup_spd);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600250#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#ifndef CONFIG_SYS_DISCOVER_PHY
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100252 set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600254#endif /* CONFIG_CMD_MII || CONFIG_MII */
255
256 /* We use strictly polling mode only */
257 fecp->eimr = 0;
258
259 /* Clear any pending interrupt */
260 fecp->eir = 0xffffffff;
261
262 /* Set station address */
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100263 if (info->index == 0)
264 rval = eth_env_get_enetaddr("ethaddr", enetaddr);
Mike Frysingerd3f87142009-02-11 19:01:26 -0500265 else
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100266 rval = eth_env_get_enetaddr("eth1addr", enetaddr);
267
268 if (!rval) {
269 puts("Please set a valid MAC address\n");
270 return -EINVAL;
271 }
272
Mike Frysingerd3f87142009-02-11 19:01:26 -0500273 fec_set_hwaddr(fecp, enetaddr);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600274
275 /* Set Opcode/Pause Duration Register */
276 fecp->opd = 0x00010020;
277
Heinrich Schuchardte4691562017-08-29 18:44:37 +0200278 /* Setup Buffers and Buffer Descriptors */
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100279 info->rx_idx = 0;
280 info->tx_idx = 0;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600281
282 /* Setup Receiver Buffer Descriptors (13.14.24.18)
283 * Settings: Empty, Wrap */
284 for (i = 0; i < PKTBUFSRX; i++) {
285 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
286 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500287 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600288 }
289 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
290
291 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
292 * Settings: Last, Tx CRC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600294 info->txbd[i].cbd_sc = 0;
295 info->txbd[i].cbd_datlen = 0;
296 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
297 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600299
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100300 info->used_tbd_idx = 0;
301 info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600302
303 /* Set Rx FIFO alarm and granularity value */
304 fecp->rfcr = 0x0c000000;
305 fecp->rfar = 0x0000030c;
306
307 /* Set Tx FIFO granularity value */
308 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
309 fecp->tfar = 0x00000080;
310
311 fecp->tfwr = 0x2;
312 fecp->ctcwr = 0x03000000;
313
314 /* Enable DMA receive task */
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100315 MCD_startDma(info->rx_task,
316 (s8 *)info->rxbd,
317 0,
318 (s8 *)&fecp->rfdr,
319 4,
320 0,
321 4,
322 info->rx_init,
323 info->rx_pri,
324 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
325 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600326 );
327
328 /* Enable DMA tx task with no ready buffer descriptors */
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100329 MCD_startDma(info->tx_task,
330 (s8 *)info->txbd,
331 0,
332 (s8 *)&fecp->tfdr,
333 4,
334 0,
335 4,
336 info->tx_init,
337 info->tx_pri,
338 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
339 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600340 );
341
342 /* Now enable the transmit and receive processing */
343 fecp->ecr |= FEC_ECR_ETHER_EN;
344
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100345 return 0;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600346}
347
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100348static int mcdmafec_init(struct udevice *dev)
349{
350 return fec_init(dev);
351}
352
353static int mcdmafec_send(struct udevice *dev, void *packet, int length)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600354{
355 struct fec_info_dma *info = dev->priv;
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100356 cbd_t *p_tbd, *p_used_tbd;
357 u16 phy_status;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600358
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100359 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600360
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100361 /* process all the consumed TBDs */
362 while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
363 p_used_tbd = &info->txbd[info->used_tbd_idx];
364 if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600365#ifdef ET_DEBUG
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100366 printf("Cannot clean TBD %d, in use\n",
367 info->clean_tbd_num);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600368#endif
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100369 return 0;
370 }
371
372 /* clean this buffer descriptor */
373 if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
374 p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
375 else
376 p_used_tbd->cbd_sc = 0;
377
378 /* update some indeces for a correct handling of TBD ring */
379 info->clean_tbd_num++;
380 info->used_tbd_idx = (info->used_tbd_idx + 1)
381 % CONFIG_SYS_TX_ETH_BUFFER;
382 }
383
384 /* Check for valid length of data. */
385 if (length > 1500 || length <= 0)
386 return -1;
387
388 /* Check the number of vacant TxBDs. */
389 if (info->clean_tbd_num < 1) {
390 printf("No available TxBDs ...\n");
391 return -1;
392 }
393
394 /* Get the first TxBD to send the mac header */
395 p_tbd = &info->txbd[info->tx_idx];
396 p_tbd->cbd_datlen = length;
397 p_tbd->cbd_bufaddr = (u32)packet;
398 p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
399 info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
400
401 /* Enable DMA transmit task */
402 MCD_continDma(info->tx_task);
403
404 info->clean_tbd_num -= 1;
405
406 /* wait until frame is sent . */
407 while (p_tbd->cbd_sc & BD_ENET_TX_READY)
408 udelay(10);
409
410 return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600411}
412
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100413static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600414{
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100415 struct fec_info_dma *info = dev->priv;
416 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
417
418 cbd_t *prbd = &info->rxbd[info->rx_idx];
419 u32 ievent;
420 int frame_length, len = 0;
421
422 /* Check if any critical events have happened */
423 ievent = fecp->eir;
424 if (ievent != 0) {
425 fecp->eir = ievent;
426
427 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
428 printf("fec_recv: error\n");
429 fec_halt(dev);
430 fec_init(dev);
431 return 0;
432 }
433
434 if (ievent & FEC_EIR_HBERR) {
435 /* Heartbeat error */
436 fecp->tcr |= FEC_TCR_GTS;
437 }
438
439 if (ievent & FEC_EIR_GRA) {
440 /* Graceful stop complete */
441 if (fecp->tcr & FEC_TCR_GTS) {
442 printf("fec_recv: tcr_gts\n");
443 fec_halt(dev);
444 fecp->tcr &= ~FEC_TCR_GTS;
445 fec_init(dev);
446 }
447 }
448 }
449
450 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
451 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
452 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
453 ((prbd->cbd_datlen - 4) > 14)) {
454 /* Get buffer address and size */
455 frame_length = prbd->cbd_datlen - 4;
456
457 /* Fill the buffer and pass it to upper layers */
458 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
459 frame_length);
460 len = frame_length;
461 }
462
463 /* Reset buffer descriptor as empty */
464 if (info->rx_idx == (PKTBUFSRX - 1))
465 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
466 else
467 prbd->cbd_sc = BD_ENET_RX_EMPTY;
468
469 prbd->cbd_datlen = PKTSIZE_ALIGN;
470
471 /* Now, we have an empty RxBD, restart the DMA receive task */
472 MCD_continDma(info->rx_task);
473
474 /* Increment BD count */
475 info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
476 }
477
478 return len;
479}
480
481static void mcdmafec_halt(struct udevice *dev)
482{
483 fec_halt(dev);
484}
485
486static const struct eth_ops mcdmafec_ops = {
487 .start = mcdmafec_init,
488 .send = mcdmafec_send,
489 .recv = mcdmafec_recv,
490 .stop = mcdmafec_halt,
491};
492
493/*
494 * Boot sequence, called just after mcffec_ofdata_to_platdata,
495 * as DM way, it replaces old mcffec_initialize.
496 */
497static int mcdmafec_probe(struct udevice *dev)
498{
499 struct fec_info_dma *info = dev->priv;
500 struct eth_pdata *pdata = dev_get_platdata(dev);
501 int node = dev_of_offset(dev);
502 int retval;
503 const u32 *val;
504
505 info->index = dev->seq;
506 info->iobase = pdata->iobase;
507 info->miibase = pdata->iobase;
508 info->phy_addr = -1;
509
510 val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
511 if (val)
512 info->rx_task = fdt32_to_cpu(*val);
513
514 val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
515 if (val)
516 info->tx_task = fdt32_to_cpu(*val);
517
518 val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
519 if (val)
520 info->rx_pri = fdt32_to_cpu(*val);
521
522 val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
523 if (val)
524 info->tx_pri = fdt32_to_cpu(*val);
525
526 val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
527 if (val)
528 info->rx_init = fdt32_to_cpu(*val);
529
530 val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
531 if (val)
532 info->tx_init = fdt32_to_cpu(*val);
533
534#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
535 u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
TsiChung Liewf32f7fe2008-04-30 12:11:19 -0500536#endif
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100537 init_eth_info(info);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600538
539#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100540 info->bus = mdio_alloc();
541 if (!info->bus)
542 return -ENOMEM;
543 strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
544 info->bus->read = mcffec_miiphy_read;
545 info->bus->write = mcffec_miiphy_write;
Joe Hershberger5a49f172016-08-08 11:28:38 -0500546
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100547 retval = mdio_register(info->bus);
548 if (retval < 0)
549 return retval;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600550#endif
551
Ben Warrenb31da882008-08-26 22:12:36 -0700552 return 0;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600553}
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100554
555static int mcdmafec_remove(struct udevice *dev)
556{
557 struct fec_info_dma *priv = dev_get_priv(dev);
558
559 mdio_unregister(priv->bus);
560 mdio_free(priv->bus);
561
562 return 0;
563}
564
565/*
566 * Boot sequence, called 1st
567 */
568static int mcdmafec_ofdata_to_platdata(struct udevice *dev)
569{
570 struct eth_pdata *pdata = dev_get_platdata(dev);
571 const u32 *val;
572
Masahiro Yamada25484932020-07-17 14:36:48 +0900573 pdata->iobase = dev_read_addr(dev);
Angelo Durgehello05ffdc82019-11-15 23:54:19 +0100574 /* Default to 10Mbit/s */
575 pdata->max_speed = 10;
576
577 val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
578 if (val)
579 pdata->max_speed = fdt32_to_cpu(*val);
580
581 return 0;
582}
583
584static const struct udevice_id mcdmafec_ids[] = {
585 { .compatible = "fsl,mcf-dma-fec" },
586 { }
587};
588
589U_BOOT_DRIVER(mcffec) = {
590 .name = "mcdmafec",
591 .id = UCLASS_ETH,
592 .of_match = mcdmafec_ids,
593 .ofdata_to_platdata = mcdmafec_ofdata_to_platdata,
594 .probe = mcdmafec_probe,
595 .remove = mcdmafec_remove,
596 .ops = &mcdmafec_ops,
597 .priv_auto_alloc_size = sizeof(struct fec_info_dma),
598 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
599};