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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wu, Josh9e336902013-04-16 23:42:44 +00002/*
3 * (C) Copyright 2013 Atmel Corporation.
4 * Josh Wu <josh.wu@atmel.com>
5 *
6 * Configuation settings for the AT91SAM9N12-EK boards.
Wu, Josh9e336902013-04-16 23:42:44 +00007 */
8
9#ifndef __AT91SAM9N12_CONFIG_H_
10#define __AT91SAM9N12_CONFIG_H_
11
Wu, Josh9e336902013-04-16 23:42:44 +000012/* ARM asynchronous clock */
13#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
14#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
Wu, Josh9e336902013-04-16 23:42:44 +000015
16/* Misc CPU related */
Wu, Josh9e336902013-04-16 23:42:44 +000017
Wu, Josh9e336902013-04-16 23:42:44 +000018/* LCD */
Wu, Josh9e336902013-04-16 23:42:44 +000019#define LCD_BPP LCD_COLOR16
20#define LCD_OUTPUT_BPP 24
Wu, Josh9e336902013-04-16 23:42:44 +000021
Wu, Josh9e336902013-04-16 23:42:44 +000022#define CONFIG_SYS_SDRAM_BASE 0x20000000
23#define CONFIG_SYS_SDRAM_SIZE 0x08000000
24
25/*
26 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
27 * leaving the correct space for initial global data structure above
28 * that address while providing maximum stack area below.
29 */
30# define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yange61ed482017-09-14 11:07:42 +080031 (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Wu, Josh9e336902013-04-16 23:42:44 +000032
33/* DataFlash */
Wu, Josh9e336902013-04-16 23:42:44 +000034
35/* NAND flash */
36#ifdef CONFIG_CMD_NAND
Wu, Josh9e336902013-04-16 23:42:44 +000037#define CONFIG_SYS_MAX_NAND_DEVICE 1
38#define CONFIG_SYS_NAND_BASE 0x40000000
39#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
40#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +010041#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
42#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
Tom Rini8f1a80e2017-07-28 21:31:42 -040043#endif
Wu, Josh9e336902013-04-16 23:42:44 +000044
Wu, Josh9e336902013-04-16 23:42:44 +000045#define CONFIG_EXTRA_ENV_SETTINGS \
46 "console=console=ttyS0,115200\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -040047 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
Wu, Josh9e336902013-04-16 23:42:44 +000048 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
49 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
50
Bo Shend9bef0a2013-10-21 16:13:59 +080051/* USB host */
52#ifdef CONFIG_CMD_USB
53#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +080054#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Bo Shend9bef0a2013-10-21 16:13:59 +080055#define CONFIG_USB_OHCI_NEW
56#define CONFIG_SYS_USB_OHCI_CPU_INIT
57#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
58#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12"
59#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
Bo Shend9bef0a2013-10-21 16:13:59 +080060#endif
61
Wenyou Yang55415432017-09-14 11:07:44 +080062#ifdef CONFIG_SPI_BOOT
Wu, Josh9e336902013-04-16 23:42:44 +000063
64/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Wu, Josh9e336902013-04-16 23:42:44 +000065
Wenyou Yang55415432017-09-14 11:07:44 +080066#elif defined(CONFIG_NAND_BOOT)
Wu, Josh9e336902013-04-16 23:42:44 +000067
68/* bootstrap + u-boot + env + linux in nandflash */
Wu, Josh9e336902013-04-16 23:42:44 +000069#endif
70
Bo Shenff255e82015-03-27 14:23:36 +080071/* SPL */
Bo Shenff255e82015-03-27 14:23:36 +080072#define CONFIG_SPL_MAX_SIZE 0x6000
73#define CONFIG_SPL_STACK 0x308000
74
75#define CONFIG_SPL_BSS_START_ADDR 0x20000000
76#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
77#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
78#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
79
Bo Shenff255e82015-03-27 14:23:36 +080080#define CONFIG_SYS_MONITOR_LEN (512 << 10)
81
82#define CONFIG_SYS_MASTER_CLOCK 132096000
83#define CONFIG_SYS_AT91_PLLA 0x20953f03
84#define CONFIG_SYS_MCKR 0x1301
85#define CONFIG_SYS_MCKR_CSS 0x1302
86
Wenyou Yang55415432017-09-14 11:07:44 +080087#ifdef CONFIG_SD_BOOT
Bo Shenff255e82015-03-27 14:23:36 +080088#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Wenyou Yang55415432017-09-14 11:07:44 +080089#endif
Bo Shenff255e82015-03-27 14:23:36 +080090
Wu, Josh9e336902013-04-16 23:42:44 +000091#endif