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Bill Richardson55ae10f2012-10-20 11:44:34 +00001/*
2 * Copyright (c) 2012 The Chromium OS Authors.
Wolfgang Denk1a459662013-07-08 09:37:19 +02003 * SPDX-License-Identifier: GPL-2.0+
Bill Richardson55ae10f2012-10-20 11:44:34 +00004 */
5
6/*
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
14 *
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
Bill Richardson57be9172012-10-20 11:44:36 +000019 *
20 *
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
Bill Richardson55ae10f2012-10-20 11:44:34 +000027 */
28
29#include <common.h>
Simon Glass74141122014-10-10 07:49:18 -060030#include <dm.h>
31#include <errno.h>
32#include <fdtdec.h>
Bin Meng3ddc1c72016-02-01 01:40:47 -080033#include <pch.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000034#include <pci.h>
Simon Glass15cf75e2016-03-11 22:07:14 -070035#include <asm/cpu.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000036#include <asm/gpio.h>
37#include <asm/io.h>
Simon Glass1b4f25f2014-11-12 22:42:24 -070038#include <asm/pci.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000039
Simon Glass8b097912015-07-31 09:31:31 -060040DECLARE_GLOBAL_DATA_PTR;
41
Simon Glass74141122014-10-10 07:49:18 -060042#define GPIO_PER_BANK 32
43
Simon Glass74141122014-10-10 07:49:18 -060044struct ich6_bank_priv {
45 /* These are I/O addresses */
Bin Mengb71eec32014-12-17 15:50:38 +080046 uint16_t use_sel;
47 uint16_t io_sel;
48 uint16_t lvl;
Bin Meng770ee012017-05-07 19:52:29 -070049 u32 lvl_write_cache;
50 bool use_lvl_write_cache;
Bill Richardson57be9172012-10-20 11:44:36 +000051};
Bill Richardson55ae10f2012-10-20 11:44:34 +000052
Gabriel Huau5318f182015-05-25 22:27:37 -070053#define GPIO_USESEL_OFFSET(x) (x)
54#define GPIO_IOSEL_OFFSET(x) (x + 4)
55#define GPIO_LVL_OFFSET(x) (x + 8)
56
Bin Meng770ee012017-05-07 19:52:29 -070057static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
58 int value)
Gabriel Huau5318f182015-05-25 22:27:37 -070059{
60 u32 val;
61
Bin Meng770ee012017-05-07 19:52:29 -070062 if (bank->use_lvl_write_cache)
63 val = bank->lvl_write_cache;
64 else
65 val = inl(bank->lvl);
66
Gabriel Huau5318f182015-05-25 22:27:37 -070067 if (value)
68 val |= (1UL << offset);
69 else
70 val &= ~(1UL << offset);
Bin Meng770ee012017-05-07 19:52:29 -070071 outl(val, bank->lvl);
72 if (bank->use_lvl_write_cache)
73 bank->lvl_write_cache = val;
Gabriel Huau5318f182015-05-25 22:27:37 -070074
75 return 0;
76}
77
Gabriel Huau5318f182015-05-25 22:27:37 -070078static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
79{
80 u32 val;
81
82 if (!dir) {
83 val = inl(base);
84 val |= (1UL << offset);
85 outl(val, base);
86 } else {
87 val = inl(base);
88 val &= ~(1UL << offset);
89 outl(val, base);
90 }
91
92 return 0;
93}
94
Gabriel Huau5318f182015-05-25 22:27:37 -070095static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
96{
97 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
Bin Meng3ddc1c72016-02-01 01:40:47 -080098 u32 gpiobase;
Gabriel Huau5318f182015-05-25 22:27:37 -070099 int offset;
Bin Meng3ddc1c72016-02-01 01:40:47 -0800100 int ret;
Gabriel Huau5318f182015-05-25 22:27:37 -0700101
Bin Meng3ddc1c72016-02-01 01:40:47 -0800102 ret = pch_get_gpio_base(dev->parent, &gpiobase);
103 if (ret)
104 return ret;
105
Simon Glasse160f7d2017-01-17 16:52:55 -0700106 offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
Simon Glass74141122014-10-10 07:49:18 -0600107 if (offset == -1) {
108 debug("%s: Invalid register offset %d\n", __func__, offset);
109 return -EINVAL;
110 }
Simon Glassd6d50db2016-03-06 19:28:13 -0700111 plat->offset = offset;
Simon Glass74141122014-10-10 07:49:18 -0600112 plat->base_addr = gpiobase + offset;
Simon Glasse160f7d2017-01-17 16:52:55 -0700113 plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
Simon Glass74141122014-10-10 07:49:18 -0600114 "bank-name", NULL);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000115
Bill Richardson55ae10f2012-10-20 11:44:34 +0000116 return 0;
117}
118
Simon Glass1b4f25f2014-11-12 22:42:24 -0700119static int ich6_gpio_probe(struct udevice *dev)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000120{
Simon Glass74141122014-10-10 07:49:18 -0600121 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
Simon Glasse564f052015-03-05 12:25:20 -0700122 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass74141122014-10-10 07:49:18 -0600123 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bin Meng770ee012017-05-07 19:52:29 -0700124 const void *prop;
Bin Meng27955732014-12-12 21:05:23 +0800125
Simon Glass74141122014-10-10 07:49:18 -0600126 uc_priv->gpio_count = GPIO_PER_BANK;
127 uc_priv->bank_name = plat->bank_name;
128 bank->use_sel = plat->base_addr;
129 bank->io_sel = plat->base_addr + 4;
130 bank->lvl = plat->base_addr + 8;
131
Simon Glassda409cc2017-05-17 17:18:09 -0600132 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
Bin Meng770ee012017-05-07 19:52:29 -0700133 "use-lvl-write-cache", NULL);
134 if (prop)
135 bank->use_lvl_write_cache = true;
136 else
137 bank->use_lvl_write_cache = false;
138 bank->lvl_write_cache = 0;
139
Simon Glass74141122014-10-10 07:49:18 -0600140 return 0;
141}
142
Simon Glass1b4f25f2014-11-12 22:42:24 -0700143static int ich6_gpio_request(struct udevice *dev, unsigned offset,
144 const char *label)
Simon Glass74141122014-10-10 07:49:18 -0600145{
146 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000147 u32 tmplong;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000148
149 /*
150 * Make sure that the GPIO pin we want isn't already in use for some
151 * built-in hardware function. We have to check this for every
152 * requested pin.
153 */
Simon Glass74141122014-10-10 07:49:18 -0600154 tmplong = inl(bank->use_sel);
155 if (!(tmplong & (1UL << offset))) {
Bill Richardson57be9172012-10-20 11:44:36 +0000156 debug("%s: gpio %d is reserved for internal use\n", __func__,
Simon Glass74141122014-10-10 07:49:18 -0600157 offset);
158 return -EPERM;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000159 }
160
Bill Richardson55ae10f2012-10-20 11:44:34 +0000161 return 0;
162}
163
Simon Glass74141122014-10-10 07:49:18 -0600164static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000165{
Simon Glass74141122014-10-10 07:49:18 -0600166 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson57be9172012-10-20 11:44:36 +0000167
Simon Glasse7cc0b62015-08-22 15:58:58 -0600168 return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000169}
170
Simon Glass74141122014-10-10 07:49:18 -0600171static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
172 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000173{
Gabriel Huau5318f182015-05-25 22:27:37 -0700174 int ret;
Simon Glass74141122014-10-10 07:49:18 -0600175 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000176
Simon Glasse7cc0b62015-08-22 15:58:58 -0600177 ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
Gabriel Huau5318f182015-05-25 22:27:37 -0700178 if (ret)
179 return ret;
Axel Lin0a547452014-12-07 12:48:27 +0800180
Bin Meng770ee012017-05-07 19:52:29 -0700181 return _ich6_gpio_set_value(bank, offset, value);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000182}
183
Simon Glass74141122014-10-10 07:49:18 -0600184static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000185{
Simon Glass74141122014-10-10 07:49:18 -0600186 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000187 u32 tmplong;
Bill Richardson57be9172012-10-20 11:44:36 +0000188 int r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000189
Simon Glass74141122014-10-10 07:49:18 -0600190 tmplong = inl(bank->lvl);
Bin Meng770ee012017-05-07 19:52:29 -0700191 if (bank->use_lvl_write_cache)
192 tmplong |= bank->lvl_write_cache;
Simon Glass74141122014-10-10 07:49:18 -0600193 r = (tmplong & (1UL << offset)) ? 1 : 0;
Bill Richardson57be9172012-10-20 11:44:36 +0000194 return r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000195}
196
Simon Glass74141122014-10-10 07:49:18 -0600197static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
198 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000199{
Simon Glass74141122014-10-10 07:49:18 -0600200 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bin Meng770ee012017-05-07 19:52:29 -0700201 return _ich6_gpio_set_value(bank, offset, value);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000202}
Simon Glass74141122014-10-10 07:49:18 -0600203
204static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
205{
206 struct ich6_bank_priv *bank = dev_get_priv(dev);
207 u32 mask = 1UL << offset;
208
209 if (!(inl(bank->use_sel) & mask))
210 return GPIOF_FUNC;
211 if (inl(bank->io_sel) & mask)
212 return GPIOF_INPUT;
213 else
214 return GPIOF_OUTPUT;
215}
216
217static const struct dm_gpio_ops gpio_ich6_ops = {
218 .request = ich6_gpio_request,
219 .direction_input = ich6_gpio_direction_input,
220 .direction_output = ich6_gpio_direction_output,
221 .get_value = ich6_gpio_get_value,
222 .set_value = ich6_gpio_set_value,
223 .get_function = ich6_gpio_get_function,
224};
225
226static const struct udevice_id intel_ich6_gpio_ids[] = {
227 { .compatible = "intel,ich6-gpio" },
228 { }
229};
230
231U_BOOT_DRIVER(gpio_ich6) = {
232 .name = "gpio_ich6",
233 .id = UCLASS_GPIO,
234 .of_match = intel_ich6_gpio_ids,
235 .ops = &gpio_ich6_ops,
236 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
237 .probe = ich6_gpio_probe,
238 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
239 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
240};