blob: 46320e7f02a71a20c7ed0ce4b9e8083eca619f42 [file] [log] [blame]
Donghwa Lee6d4339f2012-04-05 19:36:17 +00001/*
2 * Copyright (C) 2012 Samsung Electronics
3 *
4 * Author: InKi Dae <inki.dae@samsung.com>
5 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Donghwa Lee6d4339f2012-04-05 19:36:17 +00008 */
9
10#include <config.h>
11#include <common.h>
Simon Glassbb5930d2016-02-21 21:09:01 -070012#include <display.h>
Simon Glass0c843582016-02-21 21:08:48 -070013#include <div64.h>
Simon Glassbb5930d2016-02-21 21:09:01 -070014#include <dm.h>
Ajay Kumarc23f3152013-02-21 23:53:01 +000015#include <fdtdec.h>
16#include <libfdt.h>
Simon Glassbb5930d2016-02-21 21:09:01 -070017#include <panel.h>
18#include <video.h>
19#include <video_bridge.h>
Donghwa Lee6d4339f2012-04-05 19:36:17 +000020#include <asm/io.h>
21#include <asm/arch/cpu.h>
22#include <asm/arch/clock.h>
23#include <asm/arch/clk.h>
24#include <asm/arch/mipi_dsim.h>
Donghwa Leea29c8322012-07-02 01:16:08 +000025#include <asm/arch/dp_info.h>
Simon Glassbb5930d2016-02-21 21:09:01 -070026#include <asm/arch/fb.h>
27#include <asm/arch/pinmux.h>
Donghwa Lee6d4339f2012-04-05 19:36:17 +000028#include <asm/arch/system.h>
Ajay Kumar9018efa2015-03-04 19:05:26 +053029#include <asm/gpio.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090030#include <linux/errno.h>
Donghwa Lee6d4339f2012-04-05 19:36:17 +000031
Ajay Kumarc23f3152013-02-21 23:53:01 +000032DECLARE_GLOBAL_DATA_PTR;
33
Simon Glassbb5930d2016-02-21 21:09:01 -070034enum {
35 FIMD_RGB_INTERFACE = 1,
36 FIMD_CPU_INTERFACE = 2,
Ajay Kumarc23f3152013-02-21 23:53:01 +000037};
Ajay Kumarc23f3152013-02-21 23:53:01 +000038
Simon Glassbb5930d2016-02-21 21:09:01 -070039enum exynos_fb_rgb_mode_t {
40 MODE_RGB_P = 0,
41 MODE_BGR_P = 1,
42 MODE_RGB_S = 2,
43 MODE_BGR_S = 3,
44};
45
46struct exynos_fb_priv {
47 ushort vl_col; /* Number of columns (i.e. 640) */
48 ushort vl_row; /* Number of rows (i.e. 480) */
49 ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
50 ushort vl_width; /* Width of display area in millimeters */
51 ushort vl_height; /* Height of display area in millimeters */
52
53 /* LCD configuration register */
54 u_char vl_freq; /* Frequency */
55 u_char vl_clkp; /* Clock polarity */
56 u_char vl_oep; /* Output Enable polarity */
57 u_char vl_hsp; /* Horizontal Sync polarity */
58 u_char vl_vsp; /* Vertical Sync polarity */
59 u_char vl_dp; /* Data polarity */
60 u_char vl_bpix; /* Bits per pixel */
61
62 /* Horizontal control register. Timing from data sheet */
63 u_char vl_hspw; /* Horz sync pulse width */
64 u_char vl_hfpd; /* Wait before of line */
65 u_char vl_hbpd; /* Wait end of line */
66
67 /* Vertical control register. */
68 u_char vl_vspw; /* Vertical sync pulse width */
69 u_char vl_vfpd; /* Wait before of frame */
70 u_char vl_vbpd; /* Wait end of frame */
71 u_char vl_cmd_allow_len; /* Wait end of frame */
72
73 unsigned int win_id;
74 unsigned int init_delay;
75 unsigned int power_on_delay;
76 unsigned int reset_delay;
77 unsigned int interface_mode;
78 unsigned int mipi_enabled;
79 unsigned int dp_enabled;
80 unsigned int cs_setup;
81 unsigned int wr_setup;
82 unsigned int wr_act;
83 unsigned int wr_hold;
84 unsigned int logo_on;
85 unsigned int logo_width;
86 unsigned int logo_height;
87 int logo_x_offset;
88 int logo_y_offset;
89 unsigned long logo_addr;
90 unsigned int rgb_mode;
91 unsigned int resolution;
92
93 /* parent clock name(MPLL, EPLL or VPLL) */
94 unsigned int pclk_name;
95 /* ratio value for source clock from parent clock. */
96 unsigned int sclk_div;
97
98 unsigned int dual_lcd_enabled;
99 struct exynos_fb *reg;
100 struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
101};
102
103static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled)
Simon Glass0c843582016-02-21 21:08:48 -0700104{
Simon Glass8b449a62016-02-21 21:09:00 -0700105 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700106 unsigned int cfg = 0;
107
108 if (enabled) {
109 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
110 EXYNOS_DUALRGB_VDEN_EN_ENABLE;
111
112 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
Simon Glass8b449a62016-02-21 21:09:00 -0700113 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) |
Simon Glass0c843582016-02-21 21:08:48 -0700114 EXYNOS_DUALRGB_MAIN_CNT(0);
115 }
116
Simon Glass8b449a62016-02-21 21:09:00 -0700117 writel(cfg, &reg->dualrgb);
Simon Glass0c843582016-02-21 21:08:48 -0700118}
119
Simon Glassbb5930d2016-02-21 21:09:01 -0700120static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv,
Simon Glass0c843582016-02-21 21:08:48 -0700121 unsigned int enabled)
122{
Simon Glass8b449a62016-02-21 21:09:00 -0700123 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700124 unsigned int cfg = 0;
125
126 if (enabled)
127 cfg = EXYNOS_DP_CLK_ENABLE;
128
Simon Glass8b449a62016-02-21 21:09:00 -0700129 writel(cfg, &reg->dp_mie_clkcon);
Simon Glass0c843582016-02-21 21:08:48 -0700130}
131
Simon Glassbb5930d2016-02-21 21:09:01 -0700132static void exynos_fimd_set_par(struct exynos_fb_priv *priv,
133 unsigned int win_id)
Simon Glass0c843582016-02-21 21:08:48 -0700134{
Simon Glass8b449a62016-02-21 21:09:00 -0700135 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700136 unsigned int cfg = 0;
137
138 /* set window control */
Simon Glass8b449a62016-02-21 21:09:00 -0700139 cfg = readl((unsigned int)&reg->wincon0 +
Simon Glass0c843582016-02-21 21:08:48 -0700140 EXYNOS_WINCON(win_id));
141
142 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
143 EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
144 EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
145 EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
146
147 /* DATAPATH is DMA */
148 cfg |= EXYNOS_WINCON_DATAPATH_DMA;
149
150 cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
151
152 /* dma burst is 16 */
153 cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
154
Simon Glass8b449a62016-02-21 21:09:00 -0700155 switch (priv->vl_bpix) {
Simon Glass0c843582016-02-21 21:08:48 -0700156 case 4:
157 cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
158 break;
159 default:
160 cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
161 break;
162 }
163
Simon Glass8b449a62016-02-21 21:09:00 -0700164 writel(cfg, (unsigned int)&reg->wincon0 +
Simon Glass0c843582016-02-21 21:08:48 -0700165 EXYNOS_WINCON(win_id));
166
167 /* set window position to x=0, y=0*/
168 cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
Simon Glass8b449a62016-02-21 21:09:00 -0700169 writel(cfg, (unsigned int)&reg->vidosd0a +
Simon Glass0c843582016-02-21 21:08:48 -0700170 EXYNOS_VIDOSD(win_id));
171
Simon Glass8b449a62016-02-21 21:09:00 -0700172 cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) |
173 EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) |
Simon Glass0c843582016-02-21 21:08:48 -0700174 EXYNOS_VIDOSD_RIGHT_X_E(1) |
175 EXYNOS_VIDOSD_BOTTOM_Y_E(0);
176
Simon Glass8b449a62016-02-21 21:09:00 -0700177 writel(cfg, (unsigned int)&reg->vidosd0b +
Simon Glass0c843582016-02-21 21:08:48 -0700178 EXYNOS_VIDOSD(win_id));
179
180 /* set window size for window0*/
Simon Glass8b449a62016-02-21 21:09:00 -0700181 cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row);
182 writel(cfg, (unsigned int)&reg->vidosd0c +
Simon Glass0c843582016-02-21 21:08:48 -0700183 EXYNOS_VIDOSD(win_id));
184}
185
Simon Glassbb5930d2016-02-21 21:09:01 -0700186static void exynos_fimd_set_buffer_address(struct exynos_fb_priv *priv,
Simon Glass0c843582016-02-21 21:08:48 -0700187 unsigned int win_id,
188 ulong lcd_base_addr)
189{
Simon Glass8b449a62016-02-21 21:09:00 -0700190 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700191 unsigned long start_addr, end_addr;
192
193 start_addr = lcd_base_addr;
Simon Glassbb5930d2016-02-21 21:09:01 -0700194 end_addr = start_addr + ((priv->vl_col * (VNBITS(priv->vl_bpix) / 8)) *
Simon Glass8b449a62016-02-21 21:09:00 -0700195 priv->vl_row);
Simon Glass0c843582016-02-21 21:08:48 -0700196
Simon Glass8b449a62016-02-21 21:09:00 -0700197 writel(start_addr, (unsigned int)&reg->vidw00add0b0 +
Simon Glass0c843582016-02-21 21:08:48 -0700198 EXYNOS_BUFFER_OFFSET(win_id));
Simon Glass8b449a62016-02-21 21:09:00 -0700199 writel(end_addr, (unsigned int)&reg->vidw00add1b0 +
Simon Glass0c843582016-02-21 21:08:48 -0700200 EXYNOS_BUFFER_OFFSET(win_id));
201}
202
Simon Glassbb5930d2016-02-21 21:09:01 -0700203static void exynos_fimd_set_clock(struct exynos_fb_priv *priv)
Simon Glass0c843582016-02-21 21:08:48 -0700204{
Simon Glass8b449a62016-02-21 21:09:00 -0700205 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700206 unsigned int cfg = 0, div = 0, remainder, remainder_div;
207 unsigned long pixel_clock;
208 unsigned long long src_clock;
209
Simon Glass8b449a62016-02-21 21:09:00 -0700210 if (priv->dual_lcd_enabled) {
211 pixel_clock = priv->vl_freq *
212 (priv->vl_hspw + priv->vl_hfpd +
213 priv->vl_hbpd + priv->vl_col / 2) *
214 (priv->vl_vspw + priv->vl_vfpd +
215 priv->vl_vbpd + priv->vl_row);
216 } else if (priv->interface_mode == FIMD_CPU_INTERFACE) {
217 pixel_clock = priv->vl_freq *
218 priv->vl_width * priv->vl_height *
219 (priv->cs_setup + priv->wr_setup +
220 priv->wr_act + priv->wr_hold + 1);
Simon Glass0c843582016-02-21 21:08:48 -0700221 } else {
Simon Glass8b449a62016-02-21 21:09:00 -0700222 pixel_clock = priv->vl_freq *
223 (priv->vl_hspw + priv->vl_hfpd +
224 priv->vl_hbpd + priv->vl_col) *
225 (priv->vl_vspw + priv->vl_vfpd +
226 priv->vl_vbpd + priv->vl_row);
Simon Glass0c843582016-02-21 21:08:48 -0700227 }
228
Simon Glass8b449a62016-02-21 21:09:00 -0700229 cfg = readl(&reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700230 cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
231 EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
232 EXYNOS_VIDCON0_CLKDIR_MASK);
233 cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
234 EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
235
236 src_clock = (unsigned long long) get_lcd_clk();
237
238 /* get quotient and remainder. */
239 remainder = do_div(src_clock, pixel_clock);
240 div = src_clock;
241
242 remainder *= 10;
243 remainder_div = remainder / pixel_clock;
244
245 /* round about one places of decimals. */
246 if (remainder_div >= 5)
247 div++;
248
249 /* in case of dual lcd mode. */
Simon Glass8b449a62016-02-21 21:09:00 -0700250 if (priv->dual_lcd_enabled)
Simon Glass0c843582016-02-21 21:08:48 -0700251 div--;
252
253 cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
Simon Glass8b449a62016-02-21 21:09:00 -0700254 writel(cfg, &reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700255}
256
Simon Glassbb5930d2016-02-21 21:09:01 -0700257void exynos_set_trigger(struct exynos_fb_priv *priv)
Simon Glass0c843582016-02-21 21:08:48 -0700258{
Simon Glass8b449a62016-02-21 21:09:00 -0700259 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700260 unsigned int cfg = 0;
261
Simon Glass8b449a62016-02-21 21:09:00 -0700262 cfg = readl(&reg->trigcon);
Simon Glass0c843582016-02-21 21:08:48 -0700263
264 cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
265
Simon Glass8b449a62016-02-21 21:09:00 -0700266 writel(cfg, &reg->trigcon);
Simon Glass0c843582016-02-21 21:08:48 -0700267}
268
Simon Glassbb5930d2016-02-21 21:09:01 -0700269int exynos_is_i80_frame_done(struct exynos_fb_priv *priv)
Simon Glass0c843582016-02-21 21:08:48 -0700270{
Simon Glass8b449a62016-02-21 21:09:00 -0700271 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700272 unsigned int cfg = 0;
273 int status;
274
Simon Glass8b449a62016-02-21 21:09:00 -0700275 cfg = readl(&reg->trigcon);
Simon Glass0c843582016-02-21 21:08:48 -0700276
277 /* frame done func is valid only when TRIMODE[0] is set to 1. */
278 status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
279 EXYNOS_I80STATUS_TRIG_DONE;
280
281 return status;
282}
283
Simon Glassbb5930d2016-02-21 21:09:01 -0700284static void exynos_fimd_lcd_on(struct exynos_fb_priv *priv)
Simon Glass0c843582016-02-21 21:08:48 -0700285{
Simon Glass8b449a62016-02-21 21:09:00 -0700286 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700287 unsigned int cfg = 0;
288
289 /* display on */
Simon Glass8b449a62016-02-21 21:09:00 -0700290 cfg = readl(&reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700291 cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
Simon Glass8b449a62016-02-21 21:09:00 -0700292 writel(cfg, &reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700293}
294
Simon Glassbb5930d2016-02-21 21:09:01 -0700295static void exynos_fimd_window_on(struct exynos_fb_priv *priv,
296 unsigned int win_id)
Simon Glass0c843582016-02-21 21:08:48 -0700297{
Simon Glass8b449a62016-02-21 21:09:00 -0700298 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700299 unsigned int cfg = 0;
300
301 /* enable window */
Simon Glass8b449a62016-02-21 21:09:00 -0700302 cfg = readl((unsigned int)&reg->wincon0 +
Simon Glass0c843582016-02-21 21:08:48 -0700303 EXYNOS_WINCON(win_id));
304 cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
Simon Glass8b449a62016-02-21 21:09:00 -0700305 writel(cfg, (unsigned int)&reg->wincon0 +
Simon Glass0c843582016-02-21 21:08:48 -0700306 EXYNOS_WINCON(win_id));
307
Simon Glass8b449a62016-02-21 21:09:00 -0700308 cfg = readl(&reg->winshmap);
Simon Glass0c843582016-02-21 21:08:48 -0700309 cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
Simon Glass8b449a62016-02-21 21:09:00 -0700310 writel(cfg, &reg->winshmap);
Simon Glass0c843582016-02-21 21:08:48 -0700311}
312
Simon Glassbb5930d2016-02-21 21:09:01 -0700313void exynos_fimd_lcd_off(struct exynos_fb_priv *priv)
Simon Glass0c843582016-02-21 21:08:48 -0700314{
Simon Glass8b449a62016-02-21 21:09:00 -0700315 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700316 unsigned int cfg = 0;
317
Simon Glass8b449a62016-02-21 21:09:00 -0700318 cfg = readl(&reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700319 cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
Simon Glass8b449a62016-02-21 21:09:00 -0700320 writel(cfg, &reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700321}
322
Simon Glassbb5930d2016-02-21 21:09:01 -0700323void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id)
Simon Glass0c843582016-02-21 21:08:48 -0700324{
Simon Glass8b449a62016-02-21 21:09:00 -0700325 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700326 unsigned int cfg = 0;
327
Simon Glass8b449a62016-02-21 21:09:00 -0700328 cfg = readl((unsigned int)&reg->wincon0 +
Simon Glass0c843582016-02-21 21:08:48 -0700329 EXYNOS_WINCON(win_id));
330 cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
Simon Glass8b449a62016-02-21 21:09:00 -0700331 writel(cfg, (unsigned int)&reg->wincon0 +
Simon Glass0c843582016-02-21 21:08:48 -0700332 EXYNOS_WINCON(win_id));
333
Simon Glass8b449a62016-02-21 21:09:00 -0700334 cfg = readl(&reg->winshmap);
Simon Glass0c843582016-02-21 21:08:48 -0700335 cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
Simon Glass8b449a62016-02-21 21:09:00 -0700336 writel(cfg, &reg->winshmap);
Simon Glass0c843582016-02-21 21:08:48 -0700337}
338
339/*
340* The reset value for FIMD SYSMMU register MMU_CTRL is 3
341* on Exynos5420 and newer versions.
342* This means FIMD SYSMMU is on by default on Exynos5420
343* and newer versions.
344* Since in u-boot we don't use SYSMMU, we should disable
345* those FIMD SYSMMU.
346* Note that there are 2 SYSMMU for FIMD: m0 and m1.
347* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
348* We disable both of them here.
349*/
350void exynos_fimd_disable_sysmmu(void)
351{
352 u32 *sysmmufimd;
353 unsigned int node;
354 int node_list[2];
355 int count;
356 int i;
357
358 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
359 COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
360 for (i = 0; i < count; i++) {
361 node = node_list[i];
362 if (node <= 0) {
363 debug("Can't get device node for fimd sysmmu\n");
364 return;
365 }
366
367 sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
368 if (!sysmmufimd) {
369 debug("Can't get base address for sysmmu fimdm0");
370 return;
371 }
372
373 writel(0x0, sysmmufimd);
374 }
375}
376
Simon Glassbb5930d2016-02-21 21:09:01 -0700377void exynos_fimd_lcd_init(struct udevice *dev)
Simon Glass0c843582016-02-21 21:08:48 -0700378{
Simon Glassbb5930d2016-02-21 21:09:01 -0700379 struct exynos_fb_priv *priv = dev_get_priv(dev);
380 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
381 struct exynos_fb *reg = priv->reg;
Simon Glass0c843582016-02-21 21:08:48 -0700382 unsigned int cfg = 0, rgb_mode;
383 unsigned int offset;
384 unsigned int node;
385
Simon Glasse160f7d2017-01-17 16:52:55 -0700386 node = dev_of_offset(dev);
Simon Glass0c843582016-02-21 21:08:48 -0700387 if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
388 exynos_fimd_disable_sysmmu();
389
390 offset = exynos_fimd_get_base_offset();
391
Simon Glass8b449a62016-02-21 21:09:00 -0700392 rgb_mode = priv->rgb_mode;
Simon Glass0c843582016-02-21 21:08:48 -0700393
Simon Glass8b449a62016-02-21 21:09:00 -0700394 if (priv->interface_mode == FIMD_RGB_INTERFACE) {
Simon Glass0c843582016-02-21 21:08:48 -0700395 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
Simon Glass8b449a62016-02-21 21:09:00 -0700396 writel(cfg, &reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700397
Simon Glass8b449a62016-02-21 21:09:00 -0700398 cfg = readl(&reg->vidcon2);
Simon Glass0c843582016-02-21 21:08:48 -0700399 cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
400 EXYNOS_VIDCON2_TVFORMATSEL_MASK |
401 EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
402 cfg |= EXYNOS_VIDCON2_WB_DISABLE;
Simon Glass8b449a62016-02-21 21:09:00 -0700403 writel(cfg, &reg->vidcon2);
Simon Glass0c843582016-02-21 21:08:48 -0700404
405 /* set polarity */
406 cfg = 0;
Simon Glass8b449a62016-02-21 21:09:00 -0700407 if (!priv->vl_clkp)
Simon Glass0c843582016-02-21 21:08:48 -0700408 cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
Simon Glass8b449a62016-02-21 21:09:00 -0700409 if (!priv->vl_hsp)
Simon Glass0c843582016-02-21 21:08:48 -0700410 cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
Simon Glass8b449a62016-02-21 21:09:00 -0700411 if (!priv->vl_vsp)
Simon Glass0c843582016-02-21 21:08:48 -0700412 cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
Simon Glass8b449a62016-02-21 21:09:00 -0700413 if (!priv->vl_dp)
Simon Glass0c843582016-02-21 21:08:48 -0700414 cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
415
Simon Glass8b449a62016-02-21 21:09:00 -0700416 writel(cfg, (unsigned int)&reg->vidcon1 + offset);
Simon Glass0c843582016-02-21 21:08:48 -0700417
418 /* set timing */
Simon Glass8b449a62016-02-21 21:09:00 -0700419 cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1);
420 cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1);
421 cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1);
422 writel(cfg, (unsigned int)&reg->vidtcon0 + offset);
Simon Glass0c843582016-02-21 21:08:48 -0700423
Simon Glass8b449a62016-02-21 21:09:00 -0700424 cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1);
425 cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1);
426 cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1);
Simon Glass0c843582016-02-21 21:08:48 -0700427
Simon Glass8b449a62016-02-21 21:09:00 -0700428 writel(cfg, (unsigned int)&reg->vidtcon1 + offset);
Simon Glass0c843582016-02-21 21:08:48 -0700429
430 /* set lcd size */
Simon Glass8b449a62016-02-21 21:09:00 -0700431 cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) |
432 EXYNOS_VIDTCON2_LINEVAL(priv->vl_row - 1) |
433 EXYNOS_VIDTCON2_HOZVAL_E(priv->vl_col - 1) |
434 EXYNOS_VIDTCON2_LINEVAL_E(priv->vl_row - 1);
Simon Glass0c843582016-02-21 21:08:48 -0700435
Simon Glass8b449a62016-02-21 21:09:00 -0700436 writel(cfg, (unsigned int)&reg->vidtcon2 + offset);
Simon Glass0c843582016-02-21 21:08:48 -0700437 }
438
439 /* set display mode */
Simon Glass8b449a62016-02-21 21:09:00 -0700440 cfg = readl(&reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700441 cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
442 cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
Simon Glass8b449a62016-02-21 21:09:00 -0700443 writel(cfg, &reg->vidcon0);
Simon Glass0c843582016-02-21 21:08:48 -0700444
445 /* set par */
Simon Glass8b449a62016-02-21 21:09:00 -0700446 exynos_fimd_set_par(priv, priv->win_id);
Simon Glass0c843582016-02-21 21:08:48 -0700447
448 /* set memory address */
Simon Glassbb5930d2016-02-21 21:09:01 -0700449 exynos_fimd_set_buffer_address(priv, priv->win_id, plat->base);
Simon Glass0c843582016-02-21 21:08:48 -0700450
451 /* set buffer size */
Simon Glass8b449a62016-02-21 21:09:00 -0700452 cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col *
Simon Glassbb5930d2016-02-21 21:09:01 -0700453 VNBITS(priv->vl_bpix) / 8) |
Simon Glass8b449a62016-02-21 21:09:00 -0700454 EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col *
Simon Glassbb5930d2016-02-21 21:09:01 -0700455 VNBITS(priv->vl_bpix) / 8) |
Simon Glass0c843582016-02-21 21:08:48 -0700456 EXYNOS_VIDADDR_OFFSIZE(0) |
457 EXYNOS_VIDADDR_OFFSIZE_E(0);
458
Simon Glass8b449a62016-02-21 21:09:00 -0700459 writel(cfg, (unsigned int)&reg->vidw00add2 +
460 EXYNOS_BUFFER_SIZE(priv->win_id));
Simon Glass0c843582016-02-21 21:08:48 -0700461
462 /* set clock */
Simon Glass8b449a62016-02-21 21:09:00 -0700463 exynos_fimd_set_clock(priv);
Simon Glass0c843582016-02-21 21:08:48 -0700464
465 /* set rgb mode to dual lcd. */
Simon Glass8b449a62016-02-21 21:09:00 -0700466 exynos_fimd_set_dualrgb(priv, priv->dual_lcd_enabled);
Simon Glass0c843582016-02-21 21:08:48 -0700467
468 /* display on */
Simon Glass8b449a62016-02-21 21:09:00 -0700469 exynos_fimd_lcd_on(priv);
Simon Glass0c843582016-02-21 21:08:48 -0700470
471 /* window on */
Simon Glass8b449a62016-02-21 21:09:00 -0700472 exynos_fimd_window_on(priv, priv->win_id);
Simon Glass0c843582016-02-21 21:08:48 -0700473
Simon Glass8b449a62016-02-21 21:09:00 -0700474 exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled);
Simon Glass0c843582016-02-21 21:08:48 -0700475}
476
Simon Glassbb5930d2016-02-21 21:09:01 -0700477unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv)
Simon Glass0c843582016-02-21 21:08:48 -0700478{
Simon Glassbb5930d2016-02-21 21:09:01 -0700479 return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000480}
481
Simon Glassbb5930d2016-02-21 21:09:01 -0700482int exynos_fb_ofdata_to_platdata(struct udevice *dev)
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000483{
Simon Glassbb5930d2016-02-21 21:09:01 -0700484 struct exynos_fb_priv *priv = dev_get_priv(dev);
Simon Glasse160f7d2017-01-17 16:52:55 -0700485 unsigned int node = dev_of_offset(dev);
Simon Glassbb5930d2016-02-21 21:09:01 -0700486 const void *blob = gd->fdt_blob;
487 fdt_addr_t addr;
Ajay Kumar9018efa2015-03-04 19:05:26 +0530488
Simon Glassbb5930d2016-02-21 21:09:01 -0700489 addr = dev_get_addr(dev);
490 if (addr == FDT_ADDR_T_NONE) {
491 debug("Can't get the FIMD base address\n");
492 return -EINVAL;
Ajay Kumar9018efa2015-03-04 19:05:26 +0530493 }
Simon Glassbb5930d2016-02-21 21:09:01 -0700494 priv->reg = (struct exynos_fb *)addr;
Ajay Kumar9018efa2015-03-04 19:05:26 +0530495
Simon Glassbb5930d2016-02-21 21:09:01 -0700496 priv->vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
497 if (priv->vl_col == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000498 debug("Can't get XRES\n");
499 return -ENXIO;
500 }
501
Simon Glassbb5930d2016-02-21 21:09:01 -0700502 priv->vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
503 if (priv->vl_row == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000504 debug("Can't get YRES\n");
505 return -ENXIO;
506 }
507
Simon Glassbb5930d2016-02-21 21:09:01 -0700508 priv->vl_width = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000509 "samsung,vl-width", 0);
510
Simon Glassbb5930d2016-02-21 21:09:01 -0700511 priv->vl_height = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000512 "samsung,vl-height", 0);
513
Simon Glassbb5930d2016-02-21 21:09:01 -0700514 priv->vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
515 if (priv->vl_freq == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000516 debug("Can't get refresh rate\n");
517 return -ENXIO;
518 }
519
520 if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
Simon Glassbb5930d2016-02-21 21:09:01 -0700521 priv->vl_clkp = VIDEO_ACTIVE_LOW;
Ajay Kumarc23f3152013-02-21 23:53:01 +0000522
523 if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
Simon Glassbb5930d2016-02-21 21:09:01 -0700524 priv->vl_oep = VIDEO_ACTIVE_LOW;
Ajay Kumarc23f3152013-02-21 23:53:01 +0000525
526 if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
Simon Glassbb5930d2016-02-21 21:09:01 -0700527 priv->vl_hsp = VIDEO_ACTIVE_LOW;
Ajay Kumarc23f3152013-02-21 23:53:01 +0000528
529 if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
Simon Glassbb5930d2016-02-21 21:09:01 -0700530 priv->vl_vsp = VIDEO_ACTIVE_LOW;
Ajay Kumarc23f3152013-02-21 23:53:01 +0000531
532 if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
Simon Glassbb5930d2016-02-21 21:09:01 -0700533 priv->vl_dp = VIDEO_ACTIVE_LOW;
Ajay Kumarc23f3152013-02-21 23:53:01 +0000534
Simon Glassbb5930d2016-02-21 21:09:01 -0700535 priv->vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
536 if (priv->vl_bpix == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000537 debug("Can't get bits per pixel\n");
538 return -ENXIO;
539 }
540
Simon Glassbb5930d2016-02-21 21:09:01 -0700541 priv->vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
542 if (priv->vl_hspw == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000543 debug("Can't get hsync width\n");
544 return -ENXIO;
545 }
546
Simon Glassbb5930d2016-02-21 21:09:01 -0700547 priv->vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
548 if (priv->vl_hfpd == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000549 debug("Can't get right margin\n");
550 return -ENXIO;
551 }
552
Simon Glassbb5930d2016-02-21 21:09:01 -0700553 priv->vl_hbpd = (u_char)fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000554 "samsung,vl-hbpd", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700555 if (priv->vl_hbpd == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000556 debug("Can't get left margin\n");
557 return -ENXIO;
558 }
559
Simon Glassbb5930d2016-02-21 21:09:01 -0700560 priv->vl_vspw = (u_char)fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000561 "samsung,vl-vspw", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700562 if (priv->vl_vspw == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000563 debug("Can't get vsync width\n");
564 return -ENXIO;
565 }
566
Simon Glassbb5930d2016-02-21 21:09:01 -0700567 priv->vl_vfpd = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000568 "samsung,vl-vfpd", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700569 if (priv->vl_vfpd == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000570 debug("Can't get lower margin\n");
571 return -ENXIO;
572 }
573
Simon Glassbb5930d2016-02-21 21:09:01 -0700574 priv->vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
575 if (priv->vl_vbpd == 0) {
Ajay Kumarc23f3152013-02-21 23:53:01 +0000576 debug("Can't get upper margin\n");
577 return -ENXIO;
578 }
579
Simon Glassbb5930d2016-02-21 21:09:01 -0700580 priv->vl_cmd_allow_len = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000581 "samsung,vl-cmd-allow-len", 0);
582
Simon Glassbb5930d2016-02-21 21:09:01 -0700583 priv->win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
584 priv->init_delay = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000585 "samsung,init-delay", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700586 priv->power_on_delay = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000587 "samsung,power-on-delay", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700588 priv->reset_delay = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000589 "samsung,reset-delay", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700590 priv->interface_mode = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000591 "samsung,interface-mode", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700592 priv->mipi_enabled = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000593 "samsung,mipi-enabled", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700594 priv->dp_enabled = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000595 "samsung,dp-enabled", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700596 priv->cs_setup = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000597 "samsung,cs-setup", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700598 priv->wr_setup = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000599 "samsung,wr-setup", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700600 priv->wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
601 priv->wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
Ajay Kumarc23f3152013-02-21 23:53:01 +0000602
Simon Glassbb5930d2016-02-21 21:09:01 -0700603 priv->logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
604 if (priv->logo_on) {
605 priv->logo_width = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000606 "samsung,logo-width", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700607 priv->logo_height = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000608 "samsung,logo-height", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700609 priv->logo_addr = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000610 "samsung,logo-addr", 0);
611 }
612
Simon Glassbb5930d2016-02-21 21:09:01 -0700613 priv->rgb_mode = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000614 "samsung,rgb-mode", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700615 priv->pclk_name = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000616 "samsung,pclk-name", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700617 priv->sclk_div = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000618 "samsung,sclk-div", 0);
Simon Glassbb5930d2016-02-21 21:09:01 -0700619 priv->dual_lcd_enabled = fdtdec_get_int(blob, node,
Ajay Kumarc23f3152013-02-21 23:53:01 +0000620 "samsung,dual-lcd-enabled", 0);
621
622 return 0;
623}
Ajay Kumarc23f3152013-02-21 23:53:01 +0000624
Simon Glassbb5930d2016-02-21 21:09:01 -0700625static int exynos_fb_probe(struct udevice *dev)
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000626{
Simon Glassbb5930d2016-02-21 21:09:01 -0700627 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
628 struct exynos_fb_priv *priv = dev_get_priv(dev);
629 struct udevice *panel, *bridge;
630 struct udevice *dp;
631 int ret;
632
633 debug("%s: start\n", __func__);
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000634 set_system_display_ctrl();
635 set_lcd_clk();
636
Piotr Wilczek1591ee72014-03-07 14:59:40 +0100637#ifdef CONFIG_EXYNOS_MIPI_DSIM
638 exynos_init_dsim_platform_data(&panel_info);
639#endif
Simon Glassbb5930d2016-02-21 21:09:01 -0700640 exynos_fimd_lcd_init(dev);
Piotr Wilczek1591ee72014-03-07 14:59:40 +0100641
Simon Glassbb5930d2016-02-21 21:09:01 -0700642 ret = uclass_first_device(UCLASS_PANEL, &panel);
643 if (ret) {
644 printf("LCD panel failed to probe\n");
645 return ret;
646 }
647 if (!panel) {
648 printf("LCD panel not found\n");
649 return -ENODEV;
Donghwa Lee90464972012-05-09 19:23:46 +0000650 }
651
Simon Glassbb5930d2016-02-21 21:09:01 -0700652 ret = uclass_first_device(UCLASS_DISPLAY, &dp);
653 if (ret) {
654 debug("%s: Display device error %d\n", __func__, ret);
655 return ret;
656 }
657 if (!dev) {
658 debug("%s: Display device missing\n", __func__);
659 return -ENODEV;
660 }
661 ret = display_enable(dp, 18, NULL);
662 if (ret) {
663 debug("%s: Display enable error %d\n", __func__, ret);
664 return ret;
665 }
666
667 /* backlight / pwm */
668 ret = panel_enable_backlight(panel);
669 if (ret) {
670 debug("%s: backlight error: %d\n", __func__, ret);
671 return ret;
672 }
673
674 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
675 if (!ret)
676 ret = video_bridge_set_backlight(bridge, 80);
677 if (ret) {
678 debug("%s: No video bridge, or no backlight on bridge\n",
679 __func__);
680 exynos_pinmux_config(PERIPH_ID_PWM0, 0);
681 }
682
683 uc_priv->xsize = priv->vl_col;
684 uc_priv->ysize = priv->vl_row;
685 uc_priv->bpix = priv->vl_bpix;
686
687 /* Enable flushing after LCD writes if requested */
688 video_set_flush_dcache(dev, true);
689
690 return 0;
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000691}
692
Simon Glassbb5930d2016-02-21 21:09:01 -0700693static int exynos_fb_bind(struct udevice *dev)
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000694{
Simon Glassbb5930d2016-02-21 21:09:01 -0700695 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
696
697 /* This is the maximum panel size we expect to see */
698 plat->size = 1920 * 1080 * 2;
699
700 return 0;
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000701}
Simon Glassbb5930d2016-02-21 21:09:01 -0700702
703static const struct video_ops exynos_fb_ops = {
704};
705
706static const struct udevice_id exynos_fb_ids[] = {
707 { .compatible = "samsung,exynos-fimd" },
708 { }
709};
710
711U_BOOT_DRIVER(exynos_fb) = {
712 .name = "exynos_fb",
713 .id = UCLASS_VIDEO,
714 .of_match = exynos_fb_ids,
715 .ops = &exynos_fb_ops,
716 .bind = exynos_fb_bind,
717 .probe = exynos_fb_probe,
718 .ofdata_to_platdata = exynos_fb_ofdata_to_platdata,
719 .priv_auto_alloc_size = sizeof(struct exynos_fb_priv),
720};