| Faiz Abbas | 41cf3cb | 2020-09-14 12:11:15 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | #ifndef __OMAP3_SPI_H_ |
| 3 | #define __OMAP3_SPI_H_ |
| 4 | |
| 5 | /* per-register bitmasks */ |
| 6 | #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) |
| 7 | #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) |
| 8 | #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) |
| 9 | #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) |
| 10 | |
| 11 | #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) |
| 12 | |
| 13 | #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) |
| 14 | #define OMAP3_MCSPI_MODULCTRL_MS BIT(2) |
| 15 | #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) |
| 16 | |
| 17 | #define OMAP3_MCSPI_CHCONF_PHA BIT(0) |
| 18 | #define OMAP3_MCSPI_CHCONF_POL BIT(1) |
| 19 | #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) |
| 20 | #define OMAP3_MCSPI_CHCONF_EPOL BIT(6) |
| 21 | #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) |
| 22 | #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
| 23 | #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) |
| 24 | #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) |
| 25 | #define OMAP3_MCSPI_CHCONF_DMAW BIT(14) |
| 26 | #define OMAP3_MCSPI_CHCONF_DMAR BIT(15) |
| 27 | #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) |
| 28 | #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) |
| 29 | #define OMAP3_MCSPI_CHCONF_IS BIT(18) |
| 30 | #define OMAP3_MCSPI_CHCONF_TURBO BIT(19) |
| 31 | #define OMAP3_MCSPI_CHCONF_FORCE BIT(20) |
| 32 | |
| 33 | #define OMAP3_MCSPI_CHSTAT_RXS BIT(0) |
| 34 | #define OMAP3_MCSPI_CHSTAT_TXS BIT(1) |
| 35 | #define OMAP3_MCSPI_CHSTAT_EOT BIT(2) |
| 36 | |
| 37 | #define OMAP3_MCSPI_CHCTRL_EN BIT(0) |
| 38 | #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) |
| 39 | |
| 40 | #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
| 41 | #define MCSPI_PINDIR_D0_IN_D1_OUT 0 |
| 42 | #define MCSPI_PINDIR_D0_OUT_D1_IN 1 |
| 43 | |
| 44 | #define OMAP3_MCSPI_MAX_FREQ 48000000 |
| 45 | #define SPI_WAIT_TIMEOUT 10 |
| 46 | |
| 47 | #define OMAP4_MCSPI_REG_OFFSET 0x100 |
| 48 | |
| 49 | /* OMAP3 McSPI registers */ |
| 50 | struct mcspi_channel { |
| 51 | unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ |
| 52 | unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */ |
| 53 | unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */ |
| 54 | unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */ |
| 55 | unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */ |
| 56 | }; |
| 57 | |
| 58 | struct mcspi { |
| 59 | unsigned char res1[0x10]; |
| 60 | unsigned int sysconfig; /* 0x10 */ |
| 61 | unsigned int sysstatus; /* 0x14 */ |
| 62 | unsigned int irqstatus; /* 0x18 */ |
| 63 | unsigned int irqenable; /* 0x1C */ |
| 64 | unsigned int wakeupenable; /* 0x20 */ |
| 65 | unsigned int syst; /* 0x24 */ |
| 66 | unsigned int modulctrl; /* 0x28 */ |
| 67 | struct mcspi_channel channel[4]; |
| 68 | /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ |
| 69 | /* channel1: 0x40 - 0x50, bus 0 & 1 */ |
| 70 | /* channel2: 0x54 - 0x64, bus 0 & 1 */ |
| 71 | /* channel3: 0x68 - 0x78, bus 0 */ |
| 72 | }; |
| 73 | |
| 74 | struct omap3_spi_plat { |
| 75 | struct mcspi *regs; |
| 76 | unsigned int pin_dir:1; |
| 77 | }; |
| 78 | #endif |