| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ROCKCHIP=y |
| 3 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 4 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 5 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 6 | CONFIG_ROCKCHIP_RK3368=y |
| 7 | CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 |
| 8 | CONFIG_TPL_LIBCOMMON_SUPPORT=y |
| 9 | CONFIG_TPL_LIBGENERIC_SUPPORT=y |
| 10 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 11 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| 12 | CONFIG_SPL_SPI_SUPPORT=y |
| 13 | CONFIG_SPL_STACK_R_ADDR=0x600000 |
| 14 | CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion" |
| 15 | CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368" |
| 16 | CONFIG_DEBUG_UART=y |
| Tom Rini | df35f45 | 2017-09-08 10:14:49 -0400 | [diff] [blame] | 17 | CONFIG_ANDROID_BOOT_IMAGE=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 18 | CONFIG_FIT=y |
| 19 | CONFIG_FIT_VERBOSE=y |
| 20 | CONFIG_SPL_LOAD_FIT=y |
| 21 | CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/lion_rk3368/fit_spl_atf.its" |
| Philipp Tomsich | c254b29 | 2017-09-11 22:04:27 +0200 | [diff] [blame] | 22 | CONFIG_BOOTSTAGE=y |
| 23 | CONFIG_SPL_BOOTSTAGE=y |
| 24 | CONFIG_BOOTSTAGE_REPORT=y |
| 25 | CONFIG_BOOTSTAGE_FDT=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 26 | # CONFIG_DISPLAY_CPUINFO is not set |
| 27 | CONFIG_ARCH_EARLY_INIT_R=y |
| 28 | CONFIG_SPL=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 29 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 30 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| 31 | # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set |
| 32 | CONFIG_TPL_SYS_MALLOC_SIMPLE=y |
| 33 | CONFIG_SPL_STACK_R=y |
| 34 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 |
| Philipp Tomsich | ec4bf3d | 2017-09-13 21:29:43 +0200 | [diff] [blame] | 35 | CONFIG_SPL_ATF=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 36 | CONFIG_TPL=y |
| 37 | CONFIG_TPL_BOOTROM_SUPPORT=y |
| 38 | CONFIG_TPL_DRIVERS_MISC_SUPPORT=y |
| Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 39 | CONFIG_CMD_GPIO=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 40 | CONFIG_CMD_MMC=y |
| 41 | CONFIG_CMD_SF=y |
| Philipp Tomsich | c254b29 | 2017-09-11 22:04:27 +0200 | [diff] [blame] | 42 | CONFIG_CMD_BOOTSTAGE=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 43 | CONFIG_CMD_REGULATOR=y |
| 44 | CONFIG_CMD_MTDPARTS=y |
| 45 | CONFIG_SPL_OF_CONTROL=y |
| 46 | CONFIG_TPL_OF_CONTROL=y |
| Philipp Tomsich | c254b29 | 2017-09-11 22:04:27 +0200 | [diff] [blame] | 47 | CONFIG_OF_LIVE=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 48 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent" |
| 49 | CONFIG_TPL_OF_PLATDATA=y |
| Tom Rini | 5dc4dfd | 2017-08-28 07:16:32 -0400 | [diff] [blame] | 50 | CONFIG_ENV_IS_IN_MMC=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 51 | CONFIG_NET_RANDOM_ETHADDR=y |
| 52 | CONFIG_TPL_DM=y |
| 53 | CONFIG_REGMAP=y |
| 54 | CONFIG_SPL_REGMAP=y |
| 55 | CONFIG_TPL_REGMAP=y |
| 56 | CONFIG_SYSCON=y |
| 57 | CONFIG_SPL_SYSCON=y |
| 58 | CONFIG_TPL_SYSCON=y |
| 59 | CONFIG_CLK=y |
| 60 | CONFIG_SPL_CLK=y |
| 61 | CONFIG_TPL_CLK=y |
| 62 | CONFIG_ROCKCHIP_GPIO=y |
| 63 | CONFIG_MMC_DW=y |
| 64 | CONFIG_MMC_DW_ROCKCHIP=y |
| 65 | CONFIG_SPI_FLASH=y |
| 66 | CONFIG_SPI_FLASH_MACRONIX=y |
| 67 | CONFIG_SPI_FLASH_WINBOND=y |
| 68 | CONFIG_PHY_MICREL=y |
| Philipp Tomsich | ed6be4f | 2017-10-30 14:44:54 +0100 | [diff] [blame] | 69 | CONFIG_PHY_MICREL_KSZ90X1=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 70 | CONFIG_DM_ETH=y |
| 71 | CONFIG_ETH_DESIGNWARE=y |
| 72 | CONFIG_RGMII=y |
| 73 | CONFIG_GMAC_ROCKCHIP=y |
| 74 | CONFIG_PINCTRL=y |
| 75 | CONFIG_SPL_PINCTRL=y |
| 76 | CONFIG_PINCTRL_ROCKCHIP_RK3368=y |
| 77 | CONFIG_DM_PMIC=y |
| 78 | CONFIG_PMIC_RK8XX=y |
| 79 | CONFIG_DM_REGULATOR_FIXED=y |
| 80 | CONFIG_RAM=y |
| 81 | CONFIG_SPL_RAM=y |
| 82 | CONFIG_TPL_RAM=y |
| 83 | CONFIG_DEBUG_UART_BASE=0xFF180000 |
| 84 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 85 | CONFIG_DEBUG_UART_SHIFT=2 |
| 86 | CONFIG_DEBUG_UART_ANNOUNCE=y |
| 87 | CONFIG_DEBUG_UART_SKIP_INIT=y |
| 88 | CONFIG_ROCKCHIP_SPI=y |
| 89 | CONFIG_SYSRESET=y |
| Philipp Tomsich | fe1c3cd | 2017-07-28 18:00:27 +0200 | [diff] [blame] | 90 | CONFIG_TIMER=y |
| 91 | CONFIG_SPL_TIMER=y |
| 92 | CONFIG_TPL_TIMER=y |
| 93 | CONFIG_ROCKCHIP_TIMER=y |
| Philipp Tomsich | 4d02d20 | 2017-07-13 01:36:39 +0200 | [diff] [blame] | 94 | CONFIG_USE_TINY_PRINTF=y |
| 95 | CONFIG_SPL_TINY_MEMSET=y |
| 96 | CONFIG_LZO=y |
| 97 | CONFIG_ERRNO_STR=y |
| 98 | CONFIG_SMBIOS_MANUFACTURER="rockchip" |