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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Dave Liu03051c32007-09-18 12:36:11 +08002 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
Eran Libertyf046ccd2005-07-28 10:08:46 -050021 */
22
23/*
24 * CPU specific code for the MPC83xx family.
25 *
26 * Derived from the MPC8260 and MPC85xx.
27 */
28
29#include <common.h>
30#include <watchdog.h>
31#include <command.h>
32#include <mpc83xx.h>
33#include <asm/processor.h>
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040034#include <libfdt.h>
Andy Fleming75b9d4a2008-08-31 16:33:26 -050035#include <tsec.h>
Ben Warren0e8454e2008-10-22 23:32:48 -070036#include <netdev.h>
Andy Fleminge1ac3872008-10-30 16:50:14 -050037#include <fsl_esdhc.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050038
Wolfgang Denkd87080b2006-03-31 18:32:53 +020039DECLARE_GLOBAL_DATA_PTR;
40
Eran Libertyf046ccd2005-07-28 10:08:46 -050041int checkcpu(void)
42{
Dave Liu5f820432006-11-03 19:33:44 -060043 volatile immap_t *immr;
Eran Libertyf046ccd2005-07-28 10:08:46 -050044 ulong clock = gd->cpu_clk;
45 u32 pvr = get_pvr();
Dave Liu5f820432006-11-03 19:33:44 -060046 u32 spridr;
Eran Libertyf046ccd2005-07-28 10:08:46 -050047 char buf[32];
Kim Phillipse5c4ade2008-03-28 10:19:07 -050048 int i;
49
Kim Phillipse5c4ade2008-03-28 10:19:07 -050050 const struct cpu_type {
51 char name[15];
52 u32 partid;
53 } cpu_type_list [] = {
54 CPU_TYPE_ENTRY(8311),
55 CPU_TYPE_ENTRY(8313),
56 CPU_TYPE_ENTRY(8314),
57 CPU_TYPE_ENTRY(8315),
58 CPU_TYPE_ENTRY(8321),
59 CPU_TYPE_ENTRY(8323),
60 CPU_TYPE_ENTRY(8343),
61 CPU_TYPE_ENTRY(8347_TBGA_),
62 CPU_TYPE_ENTRY(8347_PBGA_),
63 CPU_TYPE_ENTRY(8349),
64 CPU_TYPE_ENTRY(8358_TBGA_),
65 CPU_TYPE_ENTRY(8358_PBGA_),
66 CPU_TYPE_ENTRY(8360),
67 CPU_TYPE_ENTRY(8377),
68 CPU_TYPE_ENTRY(8378),
69 CPU_TYPE_ENTRY(8379),
70 };
Eran Libertyf046ccd2005-07-28 10:08:46 -050071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 immr = (immap_t *)CONFIG_SYS_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -060073
Kim Phillips54b2d432007-04-30 15:26:21 -050074 puts("CPU: ");
Scott Wood95e7ef82007-04-16 14:34:16 -050075
76 switch (pvr & 0xffff0000) {
77 case PVR_E300C1:
78 printf("e300c1, ");
79 break;
80
81 case PVR_E300C2:
82 printf("e300c2, ");
83 break;
84
85 case PVR_E300C3:
86 printf("e300c3, ");
87 break;
88
Dave Liu03051c32007-09-18 12:36:11 +080089 case PVR_E300C4:
90 printf("e300c4, ");
91 break;
92
Scott Wood95e7ef82007-04-16 14:34:16 -050093 default:
94 printf("Unknown core, ");
Eran Libertyf046ccd2005-07-28 10:08:46 -050095 }
96
Dave Liu5f820432006-11-03 19:33:44 -060097 spridr = immr->sysconf.spridr;
Rafal Jaworowski6902df52005-10-17 02:39:53 +020098
Kim Phillipse5c4ade2008-03-28 10:19:07 -050099 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
100 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
101 puts("MPC");
102 puts(cpu_type_list[i].name);
103 if (IS_E_PROCESSOR(spridr))
104 puts("E");
105 if (REVID_MAJOR(spridr) >= 2)
106 puts("A");
107 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
108 REVID_MINOR(spridr));
109 break;
110 }
111
112 if (i == ARRAY_SIZE(cpu_type_list))
113 printf("(SPRIDR %08x unknown), ", spridr);
114
115 printf(" at %s MHz, ", strmhz(buf, clock));
116
117 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
Kim Phillips54b2d432007-04-30 15:26:21 -0500118
Eran Libertyf046ccd2005-07-28 10:08:46 -0500119 return 0;
120}
121
122
Timur Tabibe5e6182006-11-03 19:15:00 -0600123/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600124 * Program a UPM with the code supplied in the table.
125 *
126 * The 'dummy' variable is used to increment the MAD. 'dummy' is
127 * supposed to be a pointer to the memory of the device being
128 * programmed by the UPM. The data in the MDR is written into
Selvamuthukumar97245552008-10-09 10:29:14 +0530129 * memory and the MAD is incremented every time there's a write
130 * to 'dummy'. Unfortunately, the current prototype for this
Timur Tabi2ad6b512006-10-31 18:44:42 -0600131 * function doesn't allow for passing the address of this
132 * device, and changing the prototype will break a number lots
133 * of other code, so we need to use a round-about way of finding
134 * the value for 'dummy'.
135 *
136 * The value can be extracted from the base address bits of the
137 * Base Register (BR) associated with the specific UPM. To find
138 * that BR, we need to scan all 8 BRs until we find the one that
139 * has its MSEL bits matching the UPM we want. Once we know the
140 * right BR, we can extract the base address bits from it.
141 *
142 * The MxMR and the BR and OR of the chosen bank should all be
143 * configured before calling this function.
144 *
145 * Parameters:
146 * upm: 0=UPMA, 1=UPMB, 2=UPMC
147 * table: Pointer to an array of values to program
148 * size: Number of elements in the array. Must be 64 or less.
Timur Tabibe5e6182006-11-03 19:15:00 -0600149 */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500150void upmconfig (uint upm, uint *table, uint size)
151{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Haiying Wang4e190b02008-10-29 11:05:55 -0400153 volatile fsl_lbus_t *lbus = &immap->lbus;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600154 volatile uchar *dummy = NULL;
155 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
156 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
157 uint i;
158
159 /* Scan all the banks to determine the base address of the device */
160 for (i = 0; i < 8; i++) {
161 if ((lbus->bank[i].br & BR_MSEL) == msel) {
162 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
163 break;
164 }
165 }
166
167 if (!dummy) {
168 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
169 hang();
170 }
171
172 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
173 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
174
175 for (i = 0; i < size; i++) {
176 lbus->mdr = table[i];
177 __asm__ __volatile__ ("sync");
Selvamuthukumar97245552008-10-09 10:29:14 +0530178 *dummy = 0; /* Write the value to memory and increment MAD */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600179 __asm__ __volatile__ ("sync");
Selvamuthukumar97245552008-10-09 10:29:14 +0530180 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
Timur Tabi2ad6b512006-10-31 18:44:42 -0600181 }
182
183 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
184 *mxmr &= 0xCFFFFFC0;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500185}
186
187
188int
189do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
190{
Wolfgang Denk07a25052005-08-05 19:49:35 +0200191 ulong msr;
192#ifndef MPC83xx_RESET
193 ulong addr;
194#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500197
198#ifdef MPC83xx_RESET
199 /* Interrupts and MMU off */
200 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
201
202 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
203 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
204
205 /* enable Reset Control Reg */
206 immap->reset.rpr = 0x52535445;
Marian Balakowicz6d8ae5a2006-03-14 16:12:48 +0100207 __asm__ __volatile__ ("sync");
208 __asm__ __volatile__ ("isync");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500209
210 /* confirm Reset Control Reg is enabled */
211 while(!((immap->reset.rcer) & RCER_CRE));
212
213 printf("Resetting the board.");
214 printf("\n");
215
216 udelay(200);
217
218 /* perform reset, only one bit */
Wolfgang Denk07a25052005-08-05 19:49:35 +0200219 immap->reset.rcr = RCR_SWHR;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500220
Wolfgang Denk07a25052005-08-05 19:49:35 +0200221#else /* ! MPC83xx_RESET */
222
223 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
224
225 /* Interrupts and MMU off */
226 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500227
228 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
229 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
230
231 /*
232 * Trying to execute the next instruction at a non-existing address
233 * should cause a machine check, resulting in reset
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 addr = CONFIG_SYS_RESET_ADDRESS;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500236
237 printf("resetting the board.");
238 printf("\n");
239 ((void (*)(void)) addr) ();
Wolfgang Denk07a25052005-08-05 19:49:35 +0200240#endif /* MPC83xx_RESET */
241
Eran Libertyf046ccd2005-07-28 10:08:46 -0500242 return 1;
243}
244
245
246/*
247 * Get timebase clock frequency (like cpu_clk in Hz)
248 */
249
250unsigned long get_tbclk(void)
251{
Eran Libertyf046ccd2005-07-28 10:08:46 -0500252 ulong tbclk;
253
254 tbclk = (gd->bus_clk + 3L) / 4L;
255
256 return tbclk;
257}
258
259
260#if defined(CONFIG_WATCHDOG)
261void watchdog_reset (void)
262{
Timur Tabi2ad6b512006-10-31 18:44:42 -0600263 int re_enable = disable_interrupts();
264
265 /* Reset the 83xx watchdog */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600267 immr->wdt.swsrr = 0x556c;
268 immr->wdt.swsrr = 0xaa39;
269
270 if (re_enable)
271 enable_interrupts ();
Eran Libertyf046ccd2005-07-28 10:08:46 -0500272}
Timur Tabi2ad6b512006-10-31 18:44:42 -0600273#endif
Kumar Gala62ec6412006-01-11 16:48:10 -0600274
Marian Balakowicz61f25152006-03-14 16:14:48 +0100275#if defined(CONFIG_DDR_ECC)
276void dma_init(void)
277{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500279 volatile dma83xx_t *dma = &immap->dma;
Marian Balakowicz61f25152006-03-14 16:14:48 +0100280 volatile u32 status = swab32(dma->dmasr0);
281 volatile u32 dmamr0 = swab32(dma->dmamr0);
282
283 debug("DMA-init\n");
284
285 /* initialize DMASARn, DMADAR and DMAABCRn */
286 dma->dmadar0 = (u32)0;
287 dma->dmasar0 = (u32)0;
288 dma->dmabcr0 = 0;
289
290 __asm__ __volatile__ ("sync");
291 __asm__ __volatile__ ("isync");
292
293 /* clear CS bit */
294 dmamr0 &= ~DMA_CHANNEL_START;
295 dma->dmamr0 = swab32(dmamr0);
296 __asm__ __volatile__ ("sync");
297 __asm__ __volatile__ ("isync");
298
299 /* while the channel is busy, spin */
300 while(status & DMA_CHANNEL_BUSY) {
301 status = swab32(dma->dmasr0);
302 }
303
304 debug("DMA-init end\n");
305}
306
307uint dma_check(void)
308{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500310 volatile dma83xx_t *dma = &immap->dma;
Marian Balakowicz61f25152006-03-14 16:14:48 +0100311 volatile u32 status = swab32(dma->dmasr0);
312 volatile u32 byte_count = swab32(dma->dmabcr0);
313
314 /* while the channel is busy, spin */
315 while (status & DMA_CHANNEL_BUSY) {
316 status = swab32(dma->dmasr0);
317 }
318
319 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
320 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
321 }
322
323 return status;
324}
325
326int dma_xfer(void *dest, u32 count, void *src)
327{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500329 volatile dma83xx_t *dma = &immap->dma;
Marian Balakowicz61f25152006-03-14 16:14:48 +0100330 volatile u32 dmamr0;
331
332 /* initialize DMASARn, DMADAR and DMAABCRn */
333 dma->dmadar0 = swab32((u32)dest);
334 dma->dmasar0 = swab32((u32)src);
335 dma->dmabcr0 = swab32(count);
336
337 __asm__ __volatile__ ("sync");
338 __asm__ __volatile__ ("isync");
339
340 /* init direct transfer, clear CS bit */
341 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
342 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
343 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200344
Marian Balakowicz61f25152006-03-14 16:14:48 +0100345 dma->dmamr0 = swab32(dmamr0);
346
347 __asm__ __volatile__ ("sync");
348 __asm__ __volatile__ ("isync");
349
350 /* set CS to start DMA transfer */
351 dmamr0 |= DMA_CHANNEL_START;
352 dma->dmamr0 = swab32(dmamr0);
353 __asm__ __volatile__ ("sync");
354 __asm__ __volatile__ ("isync");
355
356 return ((int)dma_check());
357}
358#endif /*CONFIG_DDR_ECC*/
Ben Warrendd354792008-06-23 22:57:27 -0700359
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500360/*
361 * Initializes on-chip ethernet controllers.
362 * to override, implement board_eth_init()
Ben Warrendd354792008-06-23 22:57:27 -0700363 */
Ben Warrendd354792008-06-23 22:57:27 -0700364int cpu_eth_init(bd_t *bis)
365{
Ben Warren0e8454e2008-10-22 23:32:48 -0700366#if defined(CONFIG_UEC_ETH1)
367 uec_initialize(0);
368#endif
369#if defined(CONFIG_UEC_ETH2)
370 uec_initialize(1);
371#endif
372#if defined(CONFIG_UEC_ETH3)
373 uec_initialize(2);
374#endif
375#if defined(CONFIG_UEC_ETH4)
376 uec_initialize(3);
377#endif
378#if defined(CONFIG_UEC_ETH5)
379 uec_initialize(4);
380#endif
381#if defined(CONFIG_UEC_ETH6)
382 uec_initialize(5);
383#endif
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500384#if defined(CONFIG_TSEC_ENET)
385 tsec_standard_init(bis);
Ben Warrendd354792008-06-23 22:57:27 -0700386#endif
Ben Warrendd354792008-06-23 22:57:27 -0700387 return 0;
388}
Andy Fleminge1ac3872008-10-30 16:50:14 -0500389
390/*
391 * Initializes on-chip MMC controllers.
392 * to override, implement board_mmc_init()
393 */
394int cpu_mmc_init(bd_t *bis)
395{
396#ifdef CONFIG_FSL_ESDHC
397 return fsl_esdhc_mmc_init(bis);
398#else
399 return 0;
400#endif
401}