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Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +09001/*
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +09002 modified from SH-IPL+g
3 Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
4
Wolfgang Denk61fb15c52007-12-27 01:52:50 +01005 Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
6
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +09007 Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
8
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090026*/
27
28#include <config.h>
29#include <version.h>
30
31#include <asm/processor.h>
32
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090033#ifdef CONFIG_CPU_SH7751
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090034#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
35#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090036#ifdef CONFIG_MARUBUN_PCCARD
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090037#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
38 A3:2 A2:15 A1:15 A0:6 A0B:7 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090039#else /* CONFIG_MARUBUN_PCCARD */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090040#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
41 A3:2 A2:15 A1:15 A0:6 A0B:7 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090042#endif /* CONFIG_MARUBUN_PCCARD */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090043#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
44 A2: 1-3 A1: 1-3 A0: 0-1 */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090045#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
46#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
47#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
48#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090049#else /* CONFIG_CPU_SH7751 */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090050#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
51#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
52#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
53 A3:2 A2:15 A1:15 A0:15 A0B:7 */
54#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
55 A2: 1-3 A1: 1-3 A0: 0-1 */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090056#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
57#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
58#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
59#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090060#endif /* CONFIG_CPU_SH7751 */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090061
62 .global lowlevel_init
63 .text
64 .align 2
65
66lowlevel_init:
67
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090068 mov.l CCR_A, r1 ! CCR Address
69 mov.l CCR_D_DISABLE, r0 ! CCR Data
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090070 mov.l r0, @r1
71
72init_bsc:
73 mov.l FRQCR_A,r1 /* FRQCR Address */
74 mov.l FRQCR_D,r0 /* FRQCR Data */
75 mov.w r0,@r1
76
77 mov.l BCR1_A,r1 /* BCR1 Address */
78 mov.l BCR1_D,r0 /* BCR1 Data */
79 mov.l r0,@r1
80
81 mov.l BCR2_A,r1 /* BCR2 Address */
82 mov.l BCR2_D,r0 /* BCR2 Data */
83 mov.w r0,@r1
84
85 mov.l WCR1_A,r1 /* WCR1 Address */
86 mov.l WCR1_D,r0 /* WCR1 Data */
87 mov.l r0,@r1
88
89 mov.l WCR2_A,r1 /* WCR2 Address */
90 mov.l WCR2_D,r0 /* WCR2 Data */
91 mov.l r0,@r1
92
93 mov.l WCR3_A,r1 /* WCR3 Address */
94 mov.l WCR3_D,r0 /* WCR3 Data */
95 mov.l r0,@r1
96
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090097 mov.l MCR_A,r1 /* MCR Address */
98 mov.l MCR_D1,r0 /* MCR Data1 */
99 mov.l r0,@r1
100
101 mov.l SDMR3_A,r1 /* Set SDRAM mode */
102 mov #0,r0
103 mov.b r0,@r1
104
Wolfgang Denk61fb15c52007-12-27 01:52:50 +0100105 ! Do you need PCMCIA setting?
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900106 ! If so, please add the lines here...
107
108 mov.l RTCNT_A,r1 /* RTCNT Address */
109 mov.l RTCNT_D,r0 /* RTCNT Data */
110 mov.w r0,@r1
111
112 mov.l RTCOR_A,r1 /* RTCOR Address */
113 mov.l RTCOR_D,r0 /* RTCOR Data */
114 mov.w r0,@r1
115
116 mov.l RTCSR_A,r1 /* RTCSR Address */
117 mov.l RTCSR_D,r0 /* RTCSR Data */
118 mov.w r0,@r1
119
120 mov.l RFCR_A,r1 /* RFCR Address */
121 mov.l RFCR_D,r0 /* RFCR Data */
122 mov.w r0,@r1 /* Clear reflesh counter */
123 /* Wait DRAM refresh 30 times */
124 mov #30,r3
1251:
126 mov.w @r1,r0
127 extu.w r0,r2
128 cmp/hi r3,r2
129 bf 1b
130
131 mov.l MCR_A,r1 /* MCR Address */
132 mov.l MCR_D2,r0 /* MCR Data2 */
133 mov.l r0,@r1
134
135 mov.l SDMR3_A,r1 /* Set SDRAM mode */
136 mov #0,r0
137 mov.b r0,@r1
138
139 rts
140 nop
141
142 .align 2
143
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +0900144CCR_A: .long CCR
145CCR_D_DISABLE: .long 0x0808
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900146FRQCR_A: .long FRQCR
147FRQCR_D:
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +0900148#ifdef CONFIG_CPU_TYPE_R
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900149 .long 0x00000e1a /* 12:3:3 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +0900150#else /* CONFIG_CPU_TYPE_R */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900151#ifdef CONFIG_GOOD_SESH4
152 .long 0x00000e13 /* 6:2:1 */
153#else
154 .long 0x00000e23 /* 6:1:1 */
155#endif
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +0900156#endif /* CONFIG_CPU_TYPE_R */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900157
158BCR1_A: .long BCR1
159BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
160BCR2_A: .long BCR2
161BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
162WCR1_A: .long WCR1
163WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
164WCR2_A: .long WCR2
165WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
166WCR3_A: .long WCR3
167WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
Wolfgang Denk61fb15c52007-12-27 01:52:50 +0100168RTCSR_A: .long RTCSR
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900169RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
170RTCNT_A: .long RTCNT
171RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
172RTCOR_A: .long RTCOR
173RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
174SDMR3_A: .long SDMR3_ADDRESS
175MCR_A: .long MCR
176MCR_D1: .long MCR_D1_VALUE
177MCR_D2: .long MCR_D2_VALUE
178RFCR_A: .long RFCR
179RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */