blob: 1a116ead1b78c211e93c5f3fd8d7e00508f82885 [file] [log] [blame]
Michal Simek5da048a2007-03-27 00:32:16 +02001/*
2 * (C) Copyright 2007 Michal Simek
3 *
4 * Michal SIMEK <monstr@monstr.eu>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
Michal Simek5da048a2007-03-27 00:32:16 +020024 * CAUTION: This file is automatically generated by libgen.
Michal Simek48fbd3a2007-05-07 17:11:09 +020025 * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
Michal Simek5da048a2007-03-27 00:32:16 +020026 */
Michal Simek76316a32007-03-11 13:42:58 +010027
Michal Simek17980492007-03-26 01:39:07 +020028/* System Clock Frequency */
Michal Simek9d1d6a32007-04-21 20:53:31 +020029#define XILINX_CLOCK_FREQ 100000000
Michal Simek76316a32007-03-11 13:42:58 +010030
Michal Simekffc50f92007-05-05 18:54:42 +020031/* Microblaze is microblaze_0 */
Michal Simekfb05f6d2007-05-07 23:58:31 +020032#define XILINX_USE_MSR_INSTR 1
Michal Simek48fbd3a2007-05-07 17:11:09 +020033#define XILINX_FSL_NUMBER 3
Michal Simekffc50f92007-05-05 18:54:42 +020034
Michal Simek48fbd3a2007-05-07 17:11:09 +020035/* Interrupt controller is opb_intc_0 */
Michal Simek9d1d6a32007-04-21 20:53:31 +020036#define XILINX_INTC_BASEADDR 0x41200000
Michal Simekfb05f6d2007-05-07 23:58:31 +020037#define XILINX_INTC_NUM_INTR_INPUTS 6
Michal Simek76316a32007-03-11 13:42:58 +010038
Michal Simek48fbd3a2007-05-07 17:11:09 +020039/* Timer pheriphery is opb_timer_1 */
Michal Simek9d1d6a32007-04-21 20:53:31 +020040#define XILINX_TIMER_BASEADDR 0x41c00000
Michal Simek17980492007-03-26 01:39:07 +020041#define XILINX_TIMER_IRQ 0
Michal Simek76316a32007-03-11 13:42:58 +010042
Michal Simek48fbd3a2007-05-07 17:11:09 +020043/* Uart pheriphery is RS232_Uart */
Michal Simek9d1d6a32007-04-21 20:53:31 +020044#define XILINX_UART_BASEADDR 0x40600000
Michal Simek17980492007-03-26 01:39:07 +020045#define XILINX_UART_BAUDRATE 115200
Michal Simek76316a32007-03-11 13:42:58 +010046
Michal Simek48fbd3a2007-05-07 17:11:09 +020047/* IIC pheriphery is IIC_EEPROM */
48#define XILINX_IIC_0_BASEADDR 0x40800000
49#define XILINX_IIC_0_FREQ 100000
50#define XILINX_IIC_0_BIT 0
Michal Simek76316a32007-03-11 13:42:58 +010051
Michal Simek48fbd3a2007-05-07 17:11:09 +020052/* GPIO is LEDs_4Bit*/
53#define XILINX_GPIO_BASEADDR 0x40000000
54
55/* Flash Memory is FLASH_2Mx32 */
Michal Simek9d1d6a32007-04-21 20:53:31 +020056#define XILINX_FLASH_START 0x2c000000
Michal Simek17980492007-03-26 01:39:07 +020057#define XILINX_FLASH_SIZE 0x00800000
Michal Simek76316a32007-03-11 13:42:58 +010058
Michal Simek48fbd3a2007-05-07 17:11:09 +020059/* Main Memory is DDR_SDRAM_64Mx32 */
Michal Simek9d1d6a32007-04-21 20:53:31 +020060#define XILINX_RAM_START 0x28000000
61#define XILINX_RAM_SIZE 0x04000000
Michal Simek17980492007-03-26 01:39:07 +020062
Michal Simek48fbd3a2007-05-07 17:11:09 +020063/* Sysace Controller is SysACE_CompactFlash */
Michal Simek9d1d6a32007-04-21 20:53:31 +020064#define XILINX_SYSACE_BASEADDR 0x41800000
Michal Simek48fbd3a2007-05-07 17:11:09 +020065#define XILINX_SYSACE_HIGHADDR 0x4180ffff
Michal Simek17980492007-03-26 01:39:07 +020066#define XILINX_SYSACE_MEM_WIDTH 16
67
Michal Simek48fbd3a2007-05-07 17:11:09 +020068/* Ethernet controller is Ethernet_MAC */
Michal Simek17980492007-03-26 01:39:07 +020069#define XPAR_XEMAC_NUM_INSTANCES 1
70#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
Michal Simek9d1d6a32007-04-21 20:53:31 +020071#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
Michal Simek48fbd3a2007-05-07 17:11:09 +020072#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
Michal Simek17980492007-03-26 01:39:07 +020073#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
74#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
75#define XPAR_OPB_ETHERNET_0_MII_EXIST 1