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wdenk7d393ae2002-10-25 21:08:05 +00001/*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk7d393ae2002-10-25 21:08:05 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenk7d393ae2002-10-25 21:08:05 +000020#define CONFIG_MIP405 1 /* ...on a MIP405 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021
22#define CONFIG_SYS_TEXT_BASE 0xFFF80000
23
wdenk7d393ae2002-10-25 21:08:05 +000024/***********************************************************
wdenkf3e0de62003-06-04 15:05:30 +000025 * Note that it may also be a MIP405T board which is a subset of the
26 * MIP405
27 ***********************************************************/
28/***********************************************************
29 * WARNING:
30 * CONFIG_BOOT_PCI is only used for first boot-up and should
31 * NOT be enabled for production bootloader
32 ***********************************************************/
wdenk8bde7f72003-06-27 21:31:46 +000033/*#define CONFIG_BOOT_PCI 1*/
wdenkf3e0de62003-06-04 15:05:30 +000034/***********************************************************
wdenk7d393ae2002-10-25 21:08:05 +000035 * Clock
36 ***********************************************************/
37#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
38
wdenk7d393ae2002-10-25 21:08:05 +000039
Jon Loeliger8353e132007-07-08 14:14:17 -050040/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050041 * BOOTP options
42 */
43#define CONFIG_BOOTP_BOOTFILESIZE
44#define CONFIG_BOOTP_BOOTPATH
45#define CONFIG_BOOTP_GATEWAY
46#define CONFIG_BOOTP_HOSTNAME
47
48
49/*
Jon Loeliger8353e132007-07-08 14:14:17 -050050 * Command line configuration.
51 */
52#include <config_cmd_default.h>
wdenkf3e0de62003-06-04 15:05:30 +000053
Jon Loeliger8353e132007-07-08 14:14:17 -050054#define CONFIG_CMD_CACHE
55#define CONFIG_CMD_DATE
56#define CONFIG_CMD_DHCP
57#define CONFIG_CMD_EEPROM
58#define CONFIG_CMD_ELF
59#define CONFIG_CMD_FAT
60#define CONFIG_CMD_I2C
61#define CONFIG_CMD_IDE
62#define CONFIG_CMD_IRQ
63#define CONFIG_CMD_JFFS2
64#define CONFIG_CMD_MII
65#define CONFIG_CMD_PCI
66#define CONFIG_CMD_PING
67#define CONFIG_CMD_REGINFO
68#define CONFIG_CMD_SAVES
69#define CONFIG_CMD_BSP
70
71#if !defined(CONFIG_MIP405T)
72 #define CONFIG_CMD_USB
wdenkf3e0de62003-06-04 15:05:30 +000073#endif
74
wdenk7d393ae2002-10-25 21:08:05 +000075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_HUSH_PARSER
wdenk7d393ae2002-10-25 21:08:05 +000077/**************************************************************
78 * I2C Stuff:
79 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
80 * 0x53.
81 * The Atmel EEPROM uses 16Bit addressing.
82 ***************************************************************/
83
Dirk Eibach880540d2013-04-25 02:40:01 +000084#define CONFIG_SYS_I2C
85#define CONFIG_SYS_I2C_PPC4XX
86#define CONFIG_SYS_I2C_PPC4XX_CH0
87#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
88#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenk7d393ae2002-10-25 21:08:05 +000089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
91#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
wdenk7d393ae2002-10-25 21:08:05 +000092/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
94#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenk7d393ae2002-10-25 21:08:05 +000095 /* 64 byte page write mode using*/
96 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk7d393ae2002-10-25 21:08:05 +000098
99
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200100#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200101#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
102#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
wdenk7d393ae2002-10-25 21:08:05 +0000103
104/***************************************************************
105 * Definitions for Serial Presence Detect EEPROM address
106 * (to get SDRAM settings)
107 ***************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000108/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200109#define SDRAM_EEPROM_READ_ADDRESS 0xA1
wdenkf3e0de62003-06-04 15:05:30 +0000110*/
wdenk7d393ae2002-10-25 21:08:05 +0000111/**************************************************************
112 * Environment definitions
113 **************************************************************/
114#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
115#define CONFIG_BOOTDELAY 5
116/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2afbe4e2005-08-13 02:04:37 +0200117/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200118#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenk7d393ae2002-10-25 21:08:05 +0000119
wdenk3e386912003-04-05 00:53:31 +0000120#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenk7d393ae2002-10-25 21:08:05 +0000121#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
122
123#define CONFIG_IPADDR 10.0.0.100
124#define CONFIG_SERVERIP 10.0.0.1
125#define CONFIG_PREBOOT
126/***************************************************************
127 * defines if the console is stored in the environment
128 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenk7d393ae2002-10-25 21:08:05 +0000130/***************************************************************
131 * defines if an overwrite_console function exists
132 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
134#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenk7d393ae2002-10-25 21:08:05 +0000135/***************************************************************
136 * defines if the overwrite_console should be stored in the
137 * environment
138 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenk7d393ae2002-10-25 21:08:05 +0000140
141/**************************************************************
142 * loads config
143 *************************************************************/
144#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7d393ae2002-10-25 21:08:05 +0000146
147#define CONFIG_MISC_INIT_R
148/***********************************************************
149 * Miscellaneous configurable options
150 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger8353e132007-07-08 14:14:17 -0500152#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000154#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000156#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
158#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
159#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
162#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenk7d393ae2002-10-25 21:08:05 +0000163
Stefan Roese550650d2010-09-20 16:05:31 +0200164#define CONFIG_CONS_INDEX 1 /* Use UART0 */
165#define CONFIG_SYS_NS16550
166#define CONFIG_SYS_NS16550_SERIAL
167#define CONFIG_SYS_NS16550_REG_SIZE 1
168#define CONFIG_SYS_NS16550_CLK get_serial_clock()
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
171#define CONFIG_SYS_BASE_BAUD 916667
wdenk7d393ae2002-10-25 21:08:05 +0000172
173/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7d393ae2002-10-25 21:08:05 +0000175 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
176 57600, 115200, 230400, 460800, 921600 }
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
179#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk7d393ae2002-10-25 21:08:05 +0000180
wdenk7d393ae2002-10-25 21:08:05 +0000181/*-----------------------------------------------------------------------
182 * PCI stuff
183 *-----------------------------------------------------------------------
184 */
185#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
186#define PCI_HOST_FORCE 1 /* configure as pci host */
187#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
188
189#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000190#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenk7d393ae2002-10-25 21:08:05 +0000191#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
192#define CONFIG_PCI_PNP /* pci plug-and-play */
193 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
195#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
196#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
197#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
198#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
199#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
200#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
201#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenk7d393ae2002-10-25 21:08:05 +0000202
203/*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7d393ae2002-10-25 21:08:05 +0000207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_SDRAM_BASE 0x00000000
209#define CONFIG_SYS_FLASH_BASE 0xFFF80000
210#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
211#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
212#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenk7d393ae2002-10-25 21:08:05 +0000213
214/*
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7d393ae2002-10-25 21:08:05 +0000220/*-----------------------------------------------------------------------
221 * FLASH organization
222 */
David Müller39441b32011-12-22 13:38:21 +0100223#define CONFIG_SYS_UPDATE_FLASH_SIZE
224#define CONFIG_SYS_FLASH_PROTECTION
225#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk7d393ae2002-10-25 21:08:05 +0000226
David Müller39441b32011-12-22 13:38:21 +0100227#define CONFIG_SYS_FLASH_CFI
228#define CONFIG_FLASH_CFI_DRIVER
229
230#define CONFIG_FLASH_SHOW_PROGRESS 45
231
232#define CONFIG_SYS_MAX_FLASH_BANKS 1
233#define CONFIG_SYS_MAX_FLASH_SECT 256
wdenk7d393ae2002-10-25 21:08:05 +0000234
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200235/*
236 * JFFS2 partitions
237 *
238 */
239/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100240#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200241#define CONFIG_JFFS2_DEV "nor0"
242#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
243#define CONFIG_JFFS2_PART_OFFSET 0x00000000
244
245/* mtdparts command line support */
246/* Note: fake mtd_id used, no linux mtd map file */
247/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100248#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200249#define MTDIDS_DEFAULT "nor0=mip405-0"
250#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
251*/
wdenk63e73c92004-02-23 22:22:28 +0000252
wdenk7d393ae2002-10-25 21:08:05 +0000253/*-----------------------------------------------------------------------
wdenk63e73c92004-02-23 22:22:28 +0000254 * Logbuffer Configuration
255 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200256#undef CONFIG_LOGBUFFER /* supported but not enabled */
wdenk63e73c92004-02-23 22:22:28 +0000257/*-----------------------------------------------------------------------
258 * Bootcountlimit Configuration
259 */
260#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
261
262/*-----------------------------------------------------------------------
263 * POST Configuration
264 */
265#if 0 /* enable this if POST is desired (is supported but not enabled) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
267 CONFIG_SYS_POST_CPU | \
268 CONFIG_SYS_POST_RTC | \
269 CONFIG_SYS_POST_I2C)
wdenk63e73c92004-02-23 22:22:28 +0000270
271#endif
wdenk7d393ae2002-10-25 21:08:05 +0000272/*
273 * Init Memory Controller:
274 */
wdenk7205e402003-09-10 22:30:53 +0000275#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
276#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
277/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
278#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenk7d393ae2002-10-25 21:08:05 +0000279
wdenkc837dcb2004-01-20 23:12:12 +0000280#define CONFIG_BOARD_EARLY_INIT_F 1
David Müller39441b32011-12-22 13:38:21 +0100281#define CONFIG_BOARD_EARLY_INIT_R
wdenk7d393ae2002-10-25 21:08:05 +0000282
283/* Peripheral Bus Mapping */
284#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
285#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
286#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
287
288#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200289#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
wdenk7d393ae2002-10-25 21:08:05 +0000290
291
wdenk7d393ae2002-10-25 21:08:05 +0000292/*-----------------------------------------------------------------------
293 * Definitions for initial stack pointer and data area (in On Chip SRAM)
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_TEMP_STACK_OCM 1
296#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
297#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
298#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200299#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200300#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk63e73c92004-02-23 22:22:28 +0000301/* reserve some memory for POST and BOOT limit info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
wdenk63e73c92004-02-23 22:22:28 +0000303
wdenk63e73c92004-02-23 22:22:28 +0000304#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
wdenk63e73c92004-02-23 22:22:28 +0000306#endif
wdenk7d393ae2002-10-25 21:08:05 +0000307
wdenk7d393ae2002-10-25 21:08:05 +0000308/***********************************************************************
309 * External peripheral base address
310 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenk7d393ae2002-10-25 21:08:05 +0000312
313/***********************************************************************
314 * Last Stage Init
315 ***********************************************************************/
316#define CONFIG_LAST_STAGE_INIT
317/************************************************************
318 * Ethernet Stuff
319 ***********************************************************/
Ben Warren96e21f82008-10-27 23:50:15 -0700320#define CONFIG_PPC4xx_EMAC
wdenk7d393ae2002-10-25 21:08:05 +0000321#define CONFIG_MII 1 /* MII PHY management */
322#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenk63e73c92004-02-23 22:22:28 +0000323#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
324#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
wdenk7d393ae2002-10-25 21:08:05 +0000325/************************************************************
326 * RTC
327 ***********************************************************/
328#define CONFIG_RTC_MC146818
329#undef CONFIG_WATCHDOG /* watchdog disabled */
330
331/************************************************************
332 * IDE/ATA stuff
333 ************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000334#if defined(CONFIG_MIP405T)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
wdenkf3e0de62003-06-04 15:05:30 +0000336#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
wdenkf3e0de62003-06-04 15:05:30 +0000338#endif
339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenk7d393ae2002-10-25 21:08:05 +0000341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
343#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
344#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
345#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
346#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
347#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenk7d393ae2002-10-25 21:08:05 +0000348
349#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
350#undef CONFIG_IDE_LED /* no led for ide supported */
351#define CONFIG_IDE_RESET /* reset for ide supported... */
352#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000353#define CONFIG_SUPPORT_VFAT
wdenk7d393ae2002-10-25 21:08:05 +0000354/************************************************************
355 * ATAPI support (experimental)
356 ************************************************************/
357#define CONFIG_ATAPI /* enable ATAPI Support */
358
359/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000360 * DISK Partition support
361 ************************************************************/
362#define CONFIG_DOS_PARTITION
363#define CONFIG_MAC_PARTITION
364#define CONFIG_ISO_PARTITION /* Experimental */
365
366/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000367 * Keyboard support
368 ************************************************************/
369#undef CONFIG_ISA_KEYBOARD
370
371/************************************************************
372 * Video support
373 ************************************************************/
374#define CONFIG_VIDEO /*To enable video controller support */
375#define CONFIG_VIDEO_CT69000
376#define CONFIG_CFB_CONSOLE
377#define CONFIG_VIDEO_LOGO
378#define CONFIG_CONSOLE_EXTRA_INFO
379#define CONFIG_VGA_AS_SINGLE_DEVICE
380#define CONFIG_VIDEO_SW_CURSOR
381#undef CONFIG_VIDEO_ONBOARD
382/************************************************************
383 * USB support EXPERIMENTAL
384 ************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000385#if !defined(CONFIG_MIP405T)
wdenk7d393ae2002-10-25 21:08:05 +0000386#define CONFIG_USB_UHCI
387#define CONFIG_USB_KEYBOARD
388#define CONFIG_USB_STORAGE
389
390/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200391#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenkf3e0de62003-06-04 15:05:30 +0000392#endif
wdenk7d393ae2002-10-25 21:08:05 +0000393/************************************************************
394 * Debug support
395 ************************************************************/
Jon Loeliger8353e132007-07-08 14:14:17 -0500396#if defined(CONFIG_CMD_KGDB)
wdenk7d393ae2002-10-25 21:08:05 +0000397#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk7d393ae2002-10-25 21:08:05 +0000398#endif
399
400/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000401 * support BZIP2 compression
402 ************************************************************/
403#define CONFIG_BZIP2 1
404
405/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000406 * Ident
407 ************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000408
wdenk7d393ae2002-10-25 21:08:05 +0000409#define VERSION_TAG "released"
wdenkf3e0de62003-06-04 15:05:30 +0000410#if !defined(CONFIG_MIP405T)
411#define CONFIG_ISO_STRING "MEV-10072-001"
412#else
413#define CONFIG_ISO_STRING "MEV-10082-001"
414#endif
415
416#if !defined(CONFIG_BOOT_PCI)
417#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
418#else
419#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
420#endif
wdenk7d393ae2002-10-25 21:08:05 +0000421
422
423#endif /* __CONFIG_H */