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Michael Hennerich37aac2d2010-05-31 14:11:53 +00001/*
2 * U-boot - Configuration file for BF527 AD7160-EVAL board
3 */
4
5#ifndef __CONFIG_BF527_AD7160_EVAL_H__
6#define __CONFIG_BF527_AD7160_EVAL_H__
7
8#include <asm/config-pre.h>
9
10
11/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf527-0.2
Michael Hennerich37aac2d2010-05-31 14:11:53 +000015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 24000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 25
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x03F6
49#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
50
51#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
52#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
53#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
54
55#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
57
58
59/*
60 * NAND Settings
61 * (can't be used same time as ethernet)
62 */
63#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
64# define CONFIG_BFIN_NFC
65# define CONFIG_BFIN_NFC_BOOTROM_ECC
66#endif
67#ifdef CONFIG_BFIN_NFC
68#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
69#define CONFIG_DRIVER_NAND_BFIN
70#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
71#define CONFIG_SYS_MAX_NAND_DEVICE 1
Michael Hennerich37aac2d2010-05-31 14:11:53 +000072#endif
73
74
75/*
76 * Flash Settings
77 */
78#define CONFIG_FLASH_CFI_DRIVER
79#define CONFIG_SYS_FLASH_BASE 0x20000000
80#define CONFIG_SYS_FLASH_CFI
81#define CONFIG_SYS_FLASH_PROTECTION
82#define CONFIG_SYS_MAX_FLASH_BANKS 1
83#define CONFIG_SYS_MAX_FLASH_SECT 259
84
85
86/*
87 * SPI Settings
88 */
89#define CONFIG_BFIN_SPI
90#define CONFIG_ENV_SPI_MAX_HZ 30000000
91#define CONFIG_SF_DEFAULT_SPEED 30000000
92#define CONFIG_SPI_FLASH
93#define CONFIG_SPI_FLASH_STMICRO
94
95
96/*
97 * Env Storage Settings
98 */
99#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
100#define CONFIG_ENV_IS_IN_SPI_FLASH
101#define CONFIG_ENV_OFFSET 0x10000
102#define CONFIG_ENV_SIZE 0x2000
103#define CONFIG_ENV_SECT_SIZE 0x10000
104#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
105#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
106#define CONFIG_ENV_IS_IN_NAND
107#define CONFIG_ENV_OFFSET 0x40000
108#define CONFIG_ENV_SIZE 0x20000
109#else
110#define CONFIG_ENV_IS_IN_FLASH
111#define CONFIG_ENV_OFFSET 0x4000
112#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
113#define CONFIG_ENV_SIZE 0x2000
114#define CONFIG_ENV_SECT_SIZE 0x2000
115#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
116#endif
117
118
119/*
120 * I2C Settings
121 */
122#define CONFIG_BFIN_TWI_I2C 1
123#define CONFIG_HARD_I2C 1
124
125
126/*
127 * SPI_MMC Settings
128 */
129#define CONFIG_MMC
Mike Frysinger14dda9d2010-12-24 12:53:47 -0500130#define CONFIG_GENERIC_MMC
131#define CONFIG_MMC_SPI
Michael Hennerich37aac2d2010-05-31 14:11:53 +0000132
133
134/*
135 * Misc Settings
136 */
137#define CONFIG_MISC_INIT_R
138#define CONFIG_UART_CONSOLE 0
Masahiro Yamadae91df492014-03-05 16:59:37 +0900139#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
Michael Hennerich37aac2d2010-05-31 14:11:53 +0000140
141/*
142 * Pull in common ADI header for remaining command/environment setup
143 */
144#include <configs/bfin_adi_common.h>
145
146#endif