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Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
2 * U-boot - Configuration file for BF533 EZKIT board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_EZKIT_H__
6#define __CONFIG_BF533_EZKIT_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey.Li3f0606a2007-03-09 13:38:44 +080010
Mike Frysingercf6f4692008-06-01 09:09:48 -040011/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf533-0.3
Mike Frysingercf6f4692008-06-01 09:09:48 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
Aubrey.Li3f0606a2007-03-09 13:38:44 +080016
Aubrey.Li3f0606a2007-03-09 13:38:44 +080017
Mike Frysingercf6f4692008-06-01 09:09:48 -040018/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 27000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 22
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_SIZE 32
46/* Early EZKITs had 32megs, but later have 64megs */
47#if (CONFIG_MEM_SIZE == 64)
48# define CONFIG_MEM_ADD_WDTH 10
49#else
50# define CONFIG_MEM_ADD_WDTH 9
51#endif
52
53#define CONFIG_EBIU_SDRRC_VAL 0x398
54#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
55
56#define CONFIG_EBIU_AMGCTL_VAL 0xFF
57#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
58#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
59
60#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
61#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
62
63
64/*
65 * Network Settings
66 */
67#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070068#define CONFIG_SMC91111 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +080069#define CONFIG_SMC91111_BASE 0x20310300
Mike Frysingercf6f4692008-06-01 09:09:48 -040070#define SMC91111_EEPROM_INIT() \
71 do { \
Ben Warren7194ab82009-10-04 22:37:03 -070072 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
73 bfin_write_FIO_FLAG_C(PF1); \
74 bfin_write_FIO_FLAG_S(PF0); \
Mike Frysingercf6f4692008-06-01 09:09:48 -040075 SSYNC(); \
76 } while (0)
77#define CONFIG_HOSTNAME bf533-ezkit
78/* Uncomment next line to use fixed MAC address */
79/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +080080
81
Jon Loeligerba2351f2007-07-04 22:31:49 -050082/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040083 * Flash Settings
Jon Loeliger079a1362007-07-10 10:12:10 -050084 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040086#define CONFIG_SYS_MAX_FLASH_BANKS 3
87#define CONFIG_SYS_MAX_FLASH_SECT 40
88#define CONFIG_ENV_IS_IN_FLASH
Mike Frysinger4c5f3072009-09-21 18:04:49 -040089#define CONFIG_ENV_ADDR 0x20030000
Mike Frysingercf6f4692008-06-01 09:09:48 -040090#define CONFIG_ENV_SECT_SIZE 0x10000
Aubrey.Li3f0606a2007-03-09 13:38:44 +080091#define FLASH_TOT_SECT 40
Mike Frysingercf6f4692008-06-01 09:09:48 -040092
Aubrey.Li3f0606a2007-03-09 13:38:44 +080093
94/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040095 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080096 */
Heiko Schocherea818db2013-01-29 08:53:15 +010097#define CONFIG_SYS_I2C_SOFT
98#ifdef CONFIG_SYS_I2C_SOFT
99#define CONFIG_SYS_I2C
Mike Frysingerbeb60e72010-06-08 16:22:44 -0400100#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
101#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
Heiko Schocherea818db2013-01-29 08:53:15 +0100102#define CONFIG_SYS_I2C_SOFT_SPEED 50000
103#define CONFIG_SYS_I2C_SOFT_SLAVE 0
104#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
105#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800106
Mike Frysingercf6f4692008-06-01 09:09:48 -0400107/*
108 * Misc Settings
109 */
110#define CONFIG_MISC_INIT_R
111#define CONFIG_RTC_BFIN
112#define CONFIG_UART_CONSOLE 0
Masahiro Yamadae91df492014-03-05 16:59:37 +0900113#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
Mike Frysingercf6f4692008-06-01 09:09:48 -0400114
115/*
116 * Pull in common ADI header for remaining command/environment setup
117 */
118#include <configs/bfin_adi_common.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800119
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800120#endif