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wdenk80885a92004-02-26 23:46:20 +00001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002
6 * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc824x.h>
29#include <asm/processor.h>
30#include <asm/io.h>
31#include <pci.h>
32#include <ide.h>
33#include "piix_pci.h"
34#include "eXalion.h"
35
36int checkboard (void)
37{
38 ulong busfreq = get_bus_freq (0);
39 char buf[32];
40
41 printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
42 printf ("Built: %s at %s\n", __DATE__, __TIME__);
43 printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq));
44
45 return 0;
46}
47
48int checkflash (void)
49{
50 printf ("checkflash\n");
51 flash_init ();
52 return (0);
53}
54
55long int initdram (int board_type)
56{
57 int i, cnt;
58 volatile uchar *base = CFG_SDRAM_BASE;
59 volatile ulong *addr;
60 ulong save[32];
61 ulong val, ret = 0;
62
63 for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
64 cnt >>= 1) {
65 addr = (volatile ulong *) base + cnt;
66 save[i++] = *addr;
67 *addr = ~cnt;
68 }
69
70 addr = (volatile ulong *) base;
71 save[i] = *addr;
72 *addr = 0;
73
74 if (*addr != 0) {
75 *addr = save[i];
76 goto Done;
77 }
78
79 for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
80 addr = (volatile ulong *) base + cnt;
81 val = *addr;
82 *addr = save[--i];
83 if (val != ~cnt) {
84 ulong new_bank0_end = cnt * sizeof (long) - 1;
85 ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
86 ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
87
88 mear1 = (mear1 & 0xFFFFFF00) |
89 ((new_bank0_end & MICR_ADDR_MASK) >>
90 MICR_ADDR_SHIFT);
91 emear1 = (emear1 & 0xFFFFFF00) |
92 ((new_bank0_end & MICR_ADDR_MASK) >>
93 MICR_EADDR_SHIFT);
94 mpc824x_mpc107_setreg (MEAR1, mear1);
95 mpc824x_mpc107_setreg (EMEAR1, emear1);
96
97 ret = cnt * sizeof (long);
98 goto Done;
99 }
100 }
101
102 ret = CFG_MAX_RAM_SIZE;
103 Done:
104 return ret;
105}
106
107int misc_init_r (void)
108{
109 pci_dev_t bdf;
110 u32 val32;
111 u8 val8;
112
113 puts ("ISA: ");
114 bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
115 if (bdf == -1) {
116 puts ("Unable to find PIIX4 ISA bridge !\n");
117 hang ();
118 }
119
120 /* set device for normal ISA instead EIO */
121 pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
122 val32 |= 0x00000001;
123 pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
124 printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
125 PCI_DEV (bdf), PCI_FUNC (bdf));
126
127 puts ("ISA: ");
128 bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
129 if (bdf == -1) {
130 puts ("Unable to find PIIX4 IDE controller !\n");
131 hang ();
132 }
133
134 /* Init BMIBA register */
135 /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
136 /* val32 |= 0x1000; */
137 /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
138
139 /* Enable BUS master and IO access */
140 val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
141 pci_write_config_dword (bdf, PCI_COMMAND, val32);
142
143 /* Set latency */
144 pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
145 val8 = 0x40;
146 pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
147
148 /* Enable Primary ATA/IDE */
149 pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
150 /* val32 = 0xa307a307; */
151 val32 = 0x00008000;
152 pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
153
154
155 printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
156 PCI_DEV (bdf), PCI_FUNC (bdf));
157
158 /* Try to get FAT working... */
159 /* fat_register_read(ide_read); */
160
161
162 return (0);
163}
164
165/*
166 * Show/Init PCI devices on the specified bus number.
167 */
168
169void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
170{
171 unsigned char line;
172
173 switch (PCI_DEV (dev)) {
174 case 16:
175 line = PCI_INT_A;
176 break;
177 case 17:
178 line = PCI_INT_B;
179 break;
180 case 18:
181 line = PCI_INT_C;
182 break;
183 case 19:
184 line = PCI_INT_D;
185 break;
186#if defined (CONFIG_MPC8245)
187 case 20:
188 line = PCI_INT_A;
189 break;
190 case 21:
191 line = PCI_INT_B;
192 break;
193 case 22:
194 line = PCI_INT_NA;
195 break;
196#endif
197 default:
198 line = PCI_INT_A;
199 break;
200 }
201 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
202}
203
204
205/*
206 * Initialize PCI Devices, report devices found.
207 */
208#ifndef CONFIG_PCI_PNP
209#if defined (CONFIG_MPC8240)
210static struct pci_config_table pci_eXalion_config_table[] = {
211 {
212 /* Intel 82559ER ethernet controller */
213 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
214 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
215 PCI_ENET0_MEMADDR,
216 PCI_COMMAND_MEMORY |
217 PCI_COMMAND_MASTER}},
218 {
219 /* Intel 82371AB PIIX4 PCI to ISA bridge */
220 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
221 pci_cfgfunc_config_device, {0,
222 0,
223 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
224 {
225 /* Intel 82371AB PIIX4 IDE controller */
226 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
227 pci_cfgfunc_config_device, {0,
228 0,
229 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
230 {}
231};
232#elif defined (CONFIG_MPC8245)
233static struct pci_config_table pci_eXalion_config_table[] = {
234 {
235 /* Intel 82559ER ethernet controller */
236 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
237 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
238 PCI_ENET0_MEMADDR,
239 PCI_COMMAND_MEMORY |
240 PCI_COMMAND_MASTER}},
241 {
242 /* Intel 82559ER ethernet controller */
243 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
244 pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
245 PCI_ENET1_MEMADDR,
246 PCI_COMMAND_MEMORY |
247 PCI_COMMAND_MASTER}},
248 {
249 /* Broadcom BCM5690 Gigabit switch */
250 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
251 pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
252 PCI_ENET2_MEMADDR,
253 PCI_COMMAND_MEMORY |
254 PCI_COMMAND_MASTER}},
255 {
256 /* Broadcom BCM5690 Gigabit switch */
257 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
258 pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
259 PCI_ENET3_MEMADDR,
260 PCI_COMMAND_MEMORY |
261 PCI_COMMAND_MASTER}},
262 {
263 /* Intel 82371AB PIIX4 PCI to ISA bridge */
264 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
265 pci_cfgfunc_config_device, {0,
266 0,
267 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
268 {
269 /* Intel 82371AB PIIX4 IDE controller */
270 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
271 pci_cfgfunc_config_device, {0,
272 0,
273 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
274 {}
275};
276#else
277#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
278#endif
279
280#endif /* #ifndef CONFIG_PCI_PNP */
281
282struct pci_controller hose = {
283#ifndef CONFIG_PCI_PNP
284 config_table:pci_eXalion_config_table,
285 fixup_irq:pci_eXalion_fixup_irq,
286#endif
287};
288
289void pci_init_board (void)
290{
291 pci_mpc824x_init (&hose);
292}