Samuel Holland | e210ec0 | 2020-10-24 10:21:55 -0500 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | // Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> |
| 3 | // Based on sun50i-a64-pine64.dts, which is: |
| 4 | // Copyright (c) 2016 ARM Ltd. |
Andre Przywara | df3ebdc | 2018-07-04 14:16:39 +0100 | [diff] [blame] | 5 | |
| 6 | #include "sun50i-a64.dtsi" |
Samuel Holland | e210ec0 | 2020-10-24 10:21:55 -0500 | [diff] [blame^] | 7 | #include "sun50i-a64-cpu-opp.dtsi" |
Andre Przywara | df3ebdc | 2018-07-04 14:16:39 +0100 | [diff] [blame] | 8 | |
Andre Przywara | 1b39a18 | 2018-10-29 00:56:47 +0000 | [diff] [blame] | 9 | #include <dt-bindings/gpio/gpio.h> |
| 10 | |
Samuel Holland | e210ec0 | 2020-10-24 10:21:55 -0500 | [diff] [blame^] | 11 | &codec_analog { |
| 12 | cpvdd-supply = <®_eldo1>; |
| 13 | }; |
| 14 | |
| 15 | &cpu0 { |
| 16 | cpu-supply = <®_dcdc2>; |
| 17 | }; |
| 18 | |
| 19 | &cpu1 { |
| 20 | cpu-supply = <®_dcdc2>; |
| 21 | }; |
| 22 | |
| 23 | &cpu2 { |
| 24 | cpu-supply = <®_dcdc2>; |
| 25 | }; |
| 26 | |
| 27 | &cpu3 { |
| 28 | cpu-supply = <®_dcdc2>; |
| 29 | }; |
| 30 | |
Andre Przywara | df3ebdc | 2018-07-04 14:16:39 +0100 | [diff] [blame] | 31 | &mmc0 { |
| 32 | pinctrl-names = "default"; |
| 33 | pinctrl-0 = <&mmc0_pins>; |
| 34 | vmmc-supply = <®_dcdc1>; |
| 35 | non-removable; |
| 36 | disable-wp; |
| 37 | bus-width = <4>; |
Andre Przywara | 1b39a18 | 2018-10-29 00:56:47 +0000 | [diff] [blame] | 38 | cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ |
Andre Przywara | df3ebdc | 2018-07-04 14:16:39 +0100 | [diff] [blame] | 39 | status = "okay"; |
| 40 | }; |
| 41 | |
| 42 | &r_rsb { |
| 43 | status = "okay"; |
| 44 | |
| 45 | axp803: pmic@3a3 { |
| 46 | compatible = "x-powers,axp803"; |
| 47 | reg = <0x3a3>; |
| 48 | interrupt-parent = <&r_intc>; |
| 49 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
| 50 | }; |
| 51 | }; |
| 52 | |
Andre Przywara | 1b39a18 | 2018-10-29 00:56:47 +0000 | [diff] [blame] | 53 | &spi0 { |
| 54 | status = "okay"; |
| 55 | |
| 56 | flash@0 { |
| 57 | #address-cells = <1>; |
| 58 | #size-cells = <1>; |
| 59 | compatible = "jedec,spi-nor"; |
| 60 | reg = <0>; |
| 61 | spi-max-frequency = <40000000>; |
| 62 | }; |
| 63 | }; |
| 64 | |
Andre Przywara | df3ebdc | 2018-07-04 14:16:39 +0100 | [diff] [blame] | 65 | #include "axp803.dtsi" |
| 66 | |
| 67 | ®_aldo2 { |
| 68 | regulator-always-on; |
| 69 | regulator-min-microvolt = <1800000>; |
| 70 | regulator-max-microvolt = <3300000>; |
| 71 | regulator-name = "vcc-pl"; |
| 72 | }; |
| 73 | |
| 74 | ®_aldo3 { |
| 75 | regulator-always-on; |
| 76 | regulator-min-microvolt = <3000000>; |
| 77 | regulator-max-microvolt = <3000000>; |
| 78 | regulator-name = "vcc-pll-avcc"; |
| 79 | }; |
| 80 | |
| 81 | ®_dcdc1 { |
| 82 | regulator-always-on; |
| 83 | regulator-min-microvolt = <3300000>; |
| 84 | regulator-max-microvolt = <3300000>; |
| 85 | regulator-name = "vcc-3v3"; |
| 86 | }; |
| 87 | |
| 88 | ®_dcdc2 { |
| 89 | regulator-always-on; |
| 90 | regulator-min-microvolt = <1040000>; |
| 91 | regulator-max-microvolt = <1300000>; |
| 92 | regulator-name = "vdd-cpux"; |
| 93 | }; |
| 94 | |
| 95 | /* DCDC3 is polyphased with DCDC2 */ |
| 96 | |
| 97 | ®_dcdc5 { |
| 98 | regulator-always-on; |
| 99 | regulator-min-microvolt = <1200000>; |
| 100 | regulator-max-microvolt = <1200000>; |
| 101 | regulator-name = "vcc-dram"; |
| 102 | }; |
| 103 | |
| 104 | ®_dcdc6 { |
| 105 | regulator-always-on; |
| 106 | regulator-min-microvolt = <1100000>; |
| 107 | regulator-max-microvolt = <1100000>; |
| 108 | regulator-name = "vdd-sys"; |
| 109 | }; |
| 110 | |
| 111 | ®_eldo1 { |
| 112 | regulator-always-on; |
| 113 | regulator-min-microvolt = <1800000>; |
| 114 | regulator-max-microvolt = <1800000>; |
| 115 | regulator-name = "vdd-1v8-lpddr"; |
| 116 | }; |
| 117 | |
| 118 | ®_fldo1 { |
| 119 | regulator-min-microvolt = <1200000>; |
| 120 | regulator-max-microvolt = <1200000>; |
| 121 | regulator-name = "vcc-1v2-hsic"; |
| 122 | }; |
| 123 | |
| 124 | /* |
| 125 | * The A64 chip cannot work without this regulator off, although |
| 126 | * it seems to be only driving the AR100 core. |
| 127 | * Maybe we don't still know well about CPUs domain. |
| 128 | */ |
| 129 | ®_fldo2 { |
| 130 | regulator-always-on; |
| 131 | regulator-min-microvolt = <1100000>; |
| 132 | regulator-max-microvolt = <1100000>; |
| 133 | regulator-name = "vdd-cpus"; |
| 134 | }; |
| 135 | |
| 136 | ®_rtc_ldo { |
| 137 | regulator-name = "vcc-rtc"; |
| 138 | }; |