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wdenk43c377f2002-07-20 10:56:28 +00001/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Modified for the Samsung SMDK2410 by
8 * (C) Copyright 2002
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30
wdenk43c377f2002-07-20 10:56:28 +000031#include <config.h>
32#include <version.h>
33
34
35/* some parameters for the board */
36
37/*
38 *
39 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
40 *
41 * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
42 *
43 */
44
45#define BWSCON 0x48000000
46
47/* BWSCON */
48#define DW8 (0x0)
49#define DW16 (0x1)
50#define DW32 (0x2)
51#define WAIT (0x1<<2)
52#define UBLB (0x1<<3)
53
54#define B1_BWSCON (DW32)
55#define B2_BWSCON (DW16)
56#define B3_BWSCON (DW16 + WAIT + UBLB)
57#define B4_BWSCON (DW16)
58#define B5_BWSCON (DW16)
59#define B6_BWSCON (DW32)
60#define B7_BWSCON (DW32)
61
62/* BANK0CON */
63#define B0_Tacs 0x0 /* 0clk */
64#define B0_Tcos 0x0 /* 0clk */
65#define B0_Tacc 0x7 /* 14clk */
66#define B0_Tcoh 0x0 /* 0clk */
67#define B0_Tah 0x0 /* 0clk */
68#define B0_Tacp 0x0
69#define B0_PMC 0x0 /* normal */
70
71/* BANK1CON */
72#define B1_Tacs 0x0 /* 0clk */
73#define B1_Tcos 0x0 /* 0clk */
74#define B1_Tacc 0x7 /* 14clk */
75#define B1_Tcoh 0x0 /* 0clk */
76#define B1_Tah 0x0 /* 0clk */
77#define B1_Tacp 0x0
78#define B1_PMC 0x0
79
80#define B2_Tacs 0x0
81#define B2_Tcos 0x0
82#define B2_Tacc 0x7
83#define B2_Tcoh 0x0
84#define B2_Tah 0x0
85#define B2_Tacp 0x0
86#define B2_PMC 0x0
87
88#define B3_Tacs 0x0 /* 0clk */
89#define B3_Tcos 0x3 /* 4clk */
90#define B3_Tacc 0x7 /* 14clk */
91#define B3_Tcoh 0x1 /* 1clk */
92#define B3_Tah 0x0 /* 0clk */
93#define B3_Tacp 0x3 /* 6clk */
94#define B3_PMC 0x0 /* normal */
95
96#define B4_Tacs 0x0 /* 0clk */
97#define B4_Tcos 0x0 /* 0clk */
98#define B4_Tacc 0x7 /* 14clk */
99#define B4_Tcoh 0x0 /* 0clk */
100#define B4_Tah 0x0 /* 0clk */
101#define B4_Tacp 0x0
102#define B4_PMC 0x0 /* normal */
103
104#define B5_Tacs 0x0 /* 0clk */
105#define B5_Tcos 0x0 /* 0clk */
106#define B5_Tacc 0x7 /* 14clk */
107#define B5_Tcoh 0x0 /* 0clk */
108#define B5_Tah 0x0 /* 0clk */
109#define B5_Tacp 0x0
110#define B5_PMC 0x0 /* normal */
111
112#define B6_MT 0x3 /* SDRAM */
113#define B6_Trcd 0x1
114#define B6_SCAN 0x1 /* 9bit */
115
116#define B7_MT 0x3 /* SDRAM */
117#define B7_Trcd 0x1 /* 3clk */
118#define B7_SCAN 0x1 /* 9bit */
119
120/* REFRESH parameter */
121#define REFEN 0x1 /* Refresh enable */
122#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
123#define Trp 0x0 /* 2clk */
124#define Trc 0x3 /* 7clk */
125#define Tchr 0x2 /* 3clk */
126#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
127/**************************************/
128
129_TEXT_BASE:
130 .word TEXT_BASE
131
wdenk400558b2005-04-02 23:52:25 +0000132.globl lowlevel_init
133lowlevel_init:
wdenk43c377f2002-07-20 10:56:28 +0000134 /* memory control configuration */
135 /* make r0 relative the current location so that it */
136 /* reads SMRDATA out of FLASH rather than memory ! */
137 ldr r0, =SMRDATA
138 ldr r1, _TEXT_BASE
139 sub r0, r0, r1
140 ldr r1, =BWSCON /* Bus Width Status Controller */
141 add r2, r0, #13*4
1420:
143 ldr r3, [r0], #4
144 str r3, [r1], #4
145 cmp r2, r0
146 bne 0b
147
148 /* everything is fine now */
149 mov pc, lr
150
151 .ltorg
152/* the literal pools origin */
153
154SMRDATA:
155 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
156 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
157 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
158 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
159 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
160 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
161 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
162 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
163 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
164 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
165 .word 0x32
166 .word 0x30
167 .word 0x30