blob: 19c9244b9459bad06d9ce61d4bccb33487c28a69 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkc6097192002-11-03 00:24:07 +00008 */
9
10#ifndef _PCI_H
11#define _PCI_H
12
Minghuan Lianed5b5802015-07-10 11:35:08 +080013#define PCI_CFG_SPACE_SIZE 256
14#define PCI_CFG_SPACE_EXP_SIZE 4096
15
wdenkc6097192002-11-03 00:24:07 +000016/*
17 * Under PCI, each device has 256 bytes of configuration address space,
18 * of which the first 64 bytes are standardized as follows:
19 */
Bin Mengdac01fd2018-08-03 01:14:52 -070020#define PCI_STD_HEADER_SIZEOF 64
wdenkc6097192002-11-03 00:24:07 +000021#define PCI_VENDOR_ID 0x00 /* 16 bits */
22#define PCI_DEVICE_ID 0x02 /* 16 bits */
23#define PCI_COMMAND 0x04 /* 16 bits */
24#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
25#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
26#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
27#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
28#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
29#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
30#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
31#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
32#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
33#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
34
35#define PCI_STATUS 0x06 /* 16 bits */
36#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
37#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
38#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
39#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
40#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
41#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
42#define PCI_STATUS_DEVSEL_FAST 0x000
43#define PCI_STATUS_DEVSEL_MEDIUM 0x200
44#define PCI_STATUS_DEVSEL_SLOW 0x400
45#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
50
51#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
52 revision */
53#define PCI_REVISION_ID 0x08 /* Revision ID */
54#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
55#define PCI_CLASS_DEVICE 0x0a /* Device class */
56#define PCI_CLASS_CODE 0x0b /* Device class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000057#define PCI_CLASS_CODE_TOO_OLD 0x00
58#define PCI_CLASS_CODE_STORAGE 0x01
59#define PCI_CLASS_CODE_NETWORK 0x02
60#define PCI_CLASS_CODE_DISPLAY 0x03
61#define PCI_CLASS_CODE_MULTIMEDIA 0x04
62#define PCI_CLASS_CODE_MEMORY 0x05
63#define PCI_CLASS_CODE_BRIDGE 0x06
64#define PCI_CLASS_CODE_COMM 0x07
65#define PCI_CLASS_CODE_PERIPHERAL 0x08
66#define PCI_CLASS_CODE_INPUT 0x09
67#define PCI_CLASS_CODE_DOCKING 0x0A
68#define PCI_CLASS_CODE_PROCESSOR 0x0B
69#define PCI_CLASS_CODE_SERIAL 0x0C
70#define PCI_CLASS_CODE_WIRELESS 0x0D
71#define PCI_CLASS_CODE_I2O 0x0E
72#define PCI_CLASS_CODE_SATELLITE 0x0F
73#define PCI_CLASS_CODE_CRYPTO 0x10
74#define PCI_CLASS_CODE_DATA 0x11
75/* Base Class 0x12 - 0xFE is reserved */
76#define PCI_CLASS_CODE_OTHER 0xFF
77
wdenkc6097192002-11-03 00:24:07 +000078#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000079#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
wdenkc6097192002-11-03 00:24:07 +0000181
182#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
183#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
184#define PCI_HEADER_TYPE 0x0e /* 8 bits */
185#define PCI_HEADER_TYPE_NORMAL 0
186#define PCI_HEADER_TYPE_BRIDGE 1
187#define PCI_HEADER_TYPE_CARDBUS 2
188
189#define PCI_BIST 0x0f /* 8 bits */
190#define PCI_BIST_CODE_MASK 0x0f /* Return result */
191#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
192#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
193
194/*
195 * Base addresses specify locations in memory or I/O space.
196 * Decoded size can be determined by writing a value of
197 * 0xffffffff to the register, and reading it back. Only
198 * 1 bits are decoded.
199 */
200#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
201#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
202#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
203#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
204#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
205#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
206#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
207#define PCI_BASE_ADDRESS_SPACE_IO 0x01
208#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
211#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
212#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
213#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
Kumar Gala30e76d52008-10-21 08:36:08 -0500214#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
wdenkc6097192002-11-03 00:24:07 +0000216/* bit 1 is reserved if address_space = 1 */
217
Simon Glass37a1cf92019-09-25 08:56:06 -0600218/* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */
219#define pci_offset_to_barnum(offset) \
220 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
221
wdenkc6097192002-11-03 00:24:07 +0000222/* Header type 0 (normal devices) */
223#define PCI_CARDBUS_CIS 0x28
224#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
225#define PCI_SUBSYSTEM_ID 0x2e
226#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
227#define PCI_ROM_ADDRESS_ENABLE 0x01
Kumar Gala30e76d52008-10-21 08:36:08 -0500228#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
wdenkc6097192002-11-03 00:24:07 +0000229
230#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
231
232/* 0x35-0x3b are reserved */
233#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
234#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
235#define PCI_MIN_GNT 0x3e /* 8 bits */
236#define PCI_MAX_LAT 0x3f /* 8 bits */
237
Simon Glass5f48d792015-07-27 15:47:17 -0600238#define PCI_INTERRUPT_LINE_DISABLE 0xff
239
wdenkc6097192002-11-03 00:24:07 +0000240/* Header type 1 (PCI-to-PCI bridges) */
241#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
242#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
243#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
244#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
245#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
246#define PCI_IO_LIMIT 0x1d
247#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
248#define PCI_IO_RANGE_TYPE_16 0x00
249#define PCI_IO_RANGE_TYPE_32 0x01
250#define PCI_IO_RANGE_MASK ~0x0f
251#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
252#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
253#define PCI_MEMORY_LIMIT 0x22
254#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
255#define PCI_MEMORY_RANGE_MASK ~0x0f
256#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
257#define PCI_PREF_MEMORY_LIMIT 0x26
258#define PCI_PREF_RANGE_TYPE_MASK 0x0f
259#define PCI_PREF_RANGE_TYPE_32 0x00
260#define PCI_PREF_RANGE_TYPE_64 0x01
261#define PCI_PREF_RANGE_MASK ~0x0f
262#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
263#define PCI_PREF_LIMIT_UPPER32 0x2c
264#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
265#define PCI_IO_LIMIT_UPPER16 0x32
266/* 0x34 same as for htype 0 */
267/* 0x35-0x3b is reserved */
268#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
269/* 0x3c-0x3d are same as for htype 0 */
270#define PCI_BRIDGE_CONTROL 0x3e
271#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
272#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
273#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
274#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
275#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
276#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
277#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
278
279/* Header type 2 (CardBus bridges) */
280#define PCI_CB_CAPABILITY_LIST 0x14
281/* 0x15 reserved */
282#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
283#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
284#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
285#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
286#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
287#define PCI_CB_MEMORY_BASE_0 0x1c
288#define PCI_CB_MEMORY_LIMIT_0 0x20
289#define PCI_CB_MEMORY_BASE_1 0x24
290#define PCI_CB_MEMORY_LIMIT_1 0x28
291#define PCI_CB_IO_BASE_0 0x2c
292#define PCI_CB_IO_BASE_0_HI 0x2e
293#define PCI_CB_IO_LIMIT_0 0x30
294#define PCI_CB_IO_LIMIT_0_HI 0x32
295#define PCI_CB_IO_BASE_1 0x34
296#define PCI_CB_IO_BASE_1_HI 0x36
297#define PCI_CB_IO_LIMIT_1 0x38
298#define PCI_CB_IO_LIMIT_1_HI 0x3a
299#define PCI_CB_IO_RANGE_MASK ~0x03
300/* 0x3c-0x3d are same as for htype 0 */
301#define PCI_CB_BRIDGE_CONTROL 0x3e
302#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
303#define PCI_CB_BRIDGE_CTL_SERR 0x02
304#define PCI_CB_BRIDGE_CTL_ISA 0x04
305#define PCI_CB_BRIDGE_CTL_VGA 0x08
306#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
307#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
308#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
309#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
310#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
311#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
312#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
313#define PCI_CB_SUBSYSTEM_ID 0x42
314#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
315/* 0x48-0x7f reserved */
316
317/* Capability lists */
318
319#define PCI_CAP_LIST_ID 0 /* Capability ID */
320#define PCI_CAP_ID_PM 0x01 /* Power Management */
321#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
322#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
323#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
324#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
325#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
Bin Meng5d544f92018-08-03 01:14:51 -0700326#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
327#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
328#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
329#define PCI_CAP_ID_DBG 0x0A /* Debug port */
330#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
331#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
332#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
333#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
334#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
335#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
336#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
337#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
338#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
339#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
340#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
wdenkc6097192002-11-03 00:24:07 +0000341#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
342#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
343#define PCI_CAP_SIZEOF 4
344
345/* Power Management Registers */
346
347#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
348#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
349#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
350#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
351#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
352#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
353#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
354#define PCI_PM_CTRL 4 /* PM control and status register */
355#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
356#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
357#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
358#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
359#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
360#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
361#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
362#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
363#define PCI_PM_DATA_REGISTER 7 /* (??) */
364#define PCI_PM_SIZEOF 8
365
366/* AGP registers */
367
368#define PCI_AGP_VERSION 2 /* BCD version number */
369#define PCI_AGP_RFU 3 /* Rest of capability flags */
370#define PCI_AGP_STATUS 4 /* Status register */
371#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
372#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
373#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
374#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
375#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
376#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
377#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
378#define PCI_AGP_COMMAND 8 /* Control register */
379#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
380#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
381#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
382#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
383#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
384#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
385#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
386#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
387#define PCI_AGP_SIZEOF 12
388
Matthew McClintockf0e6f572006-06-28 10:44:49 -0500389/* PCI-X registers */
390
391#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
392#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
393#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
394#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
395#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
396
397
wdenkc6097192002-11-03 00:24:07 +0000398/* Slot Identification */
399
400#define PCI_SID_ESR 2 /* Expansion Slot Register */
401#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
402#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
403#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
404
405/* Message Signalled Interrupts registers */
406
407#define PCI_MSI_FLAGS 2 /* Various flags */
408#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
409#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
410#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
411#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
Ramon Fried8781d042019-04-06 05:12:01 +0300412#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
wdenkc6097192002-11-03 00:24:07 +0000413#define PCI_MSI_RFU 3 /* Rest of capability flags */
414#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
415#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
416#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
417#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
418
419#define PCI_MAX_PCI_DEVICES 32
420#define PCI_MAX_PCI_FUNCTIONS 8
421
Zhao Qiang287df012013-10-12 13:46:33 +0800422#define PCI_FIND_CAP_TTL 0x48
423#define CAP_START_POS 0x40
424
Minghuan Lianed5b5802015-07-10 11:35:08 +0800425/* Extended Capabilities (PCI-X 2.0 and Express) */
426#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
427#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
428#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
429
430#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
431#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
432#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
433#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
434#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
435#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
436#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
437#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
438#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
439#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
440#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
441#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
442#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
443#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
444#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
445#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
446#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
447#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
448#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
449#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
450#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
451#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
452#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
453#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
454#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
455#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
456#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
Bin Meng5d544f92018-08-03 01:14:51 -0700457#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
458#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
459#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
460#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
Minghuan Lianed5b5802015-07-10 11:35:08 +0800461
Alex Marginean0b143d82019-06-07 11:24:23 +0300462/* Enhanced Allocation Registers */
463#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
464#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
465#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
466#define PCI_EA_ES 0x00000007 /* Entry Size */
467#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
468/* Base, MaxOffset registers */
469/* bit 0 is reserved */
470#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
471#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
472
Alex Margineanb8e1f822019-06-07 11:24:25 +0300473/* PCI Express capabilities */
474#define PCI_EXP_DEVCAP 4 /* Device capabilities */
475#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
476#define PCI_EXP_DEVCTL 8 /* Device Control */
477#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
478
wdenkc6097192002-11-03 00:24:07 +0000479/* Include the ID list */
480
481#include <pci_ids.h>
482
Paul Burtonfa5cec02013-11-08 11:18:47 +0000483#ifndef __ASSEMBLY__
484
Simon Glass6dd4b012019-12-06 21:41:38 -0700485#include <dm/pci.h>
486
Kumar Gala30e76d52008-10-21 08:36:08 -0500487#ifdef CONFIG_SYS_PCI_64BIT
488typedef u64 pci_addr_t;
489typedef u64 pci_size_t;
490#else
Heinrich Schuchardt58fc2b52020-02-05 21:59:12 +0100491typedef unsigned long pci_addr_t;
492typedef unsigned long pci_size_t;
Kumar Gala30e76d52008-10-21 08:36:08 -0500493#endif
wdenkc6097192002-11-03 00:24:07 +0000494
Kumar Gala30e76d52008-10-21 08:36:08 -0500495struct pci_region {
496 pci_addr_t bus_start; /* Start on the bus */
497 phys_addr_t phys_start; /* Start in physical address space */
498 pci_size_t size; /* Size */
499 unsigned long flags; /* Resource flags */
500
501 pci_addr_t bus_lower;
wdenkc6097192002-11-03 00:24:07 +0000502};
503
504#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
505#define PCI_REGION_IO 0x00000001 /* PCI IO space */
506#define PCI_REGION_TYPE 0x00000001
Kumar Galaa1790122006-01-11 13:24:15 -0600507#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
wdenkc6097192002-11-03 00:24:07 +0000508
Kumar Galaff4e66e2009-02-06 09:49:31 -0600509#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
wdenkc6097192002-11-03 00:24:07 +0000510#define PCI_REGION_RO 0x00000200 /* Read-only memory */
511
Simon Glassbc3442a2013-06-11 11:14:33 -0700512static inline void pci_set_region(struct pci_region *reg,
Kumar Gala30e76d52008-10-21 08:36:08 -0500513 pci_addr_t bus_start,
Becky Bruce36f32672008-05-07 13:24:57 -0500514 phys_addr_t phys_start,
Kumar Gala30e76d52008-10-21 08:36:08 -0500515 pci_size_t size,
wdenkc6097192002-11-03 00:24:07 +0000516 unsigned long flags) {
517 reg->bus_start = bus_start;
518 reg->phys_start = phys_start;
519 reg->size = size;
520 reg->flags = flags;
521}
522
523typedef int pci_dev_t;
524
Simon Glassff3e0772015-03-05 12:25:25 -0700525#define PCI_BUS(d) (((d) >> 16) & 0xff)
Stefan Roese2253d642019-02-11 08:43:25 +0100526
527/*
528 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
529 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
530 * Please see the Linux header include/uapi/linux/pci.h for more details.
531 * This is relevant for the following macros:
532 * PCI_DEV, PCI_FUNC, PCI_DEVFN
533 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
Simon Glass5f20c282020-05-10 10:26:54 -0600534 * the remark from above (input is in bits 15-8 instead of 7-0.
Stefan Roese2253d642019-02-11 08:43:25 +0100535 */
Simon Glassff3e0772015-03-05 12:25:25 -0700536#define PCI_DEV(d) (((d) >> 11) & 0x1f)
537#define PCI_FUNC(d) (((d) >> 8) & 0x7)
538#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
Stefan Roese2253d642019-02-11 08:43:25 +0100539
Simon Glassff3e0772015-03-05 12:25:25 -0700540#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
541#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
542#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
543#define PCI_VENDEV(v, d) (((v) << 16) | (d))
544#define PCI_ANY_ID (~0)
wdenkc6097192002-11-03 00:24:07 +0000545
Simon Glassf0597032020-04-08 08:32:59 -0600546/* Convert from Linux format to U-Boot format */
547#define PCI_TO_BDF(val) ((val) << 8)
548
wdenkc6097192002-11-03 00:24:07 +0000549struct pci_device_id {
Simon Glassaba92962015-07-06 16:47:44 -0600550 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
551 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
552 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
553 unsigned long driver_data; /* Data private to the driver */
wdenkc6097192002-11-03 00:24:07 +0000554};
555
556struct pci_controller;
557
558struct pci_config_table {
559 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
560 unsigned int class; /* Class ID, or PCI_ANY_ID */
561 unsigned int bus; /* Bus number, or PCI_ANY_ID */
562 unsigned int dev; /* Device number, or PCI_ANY_ID */
563 unsigned int func; /* Function number, or PCI_ANY_ID */
564
565 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
566 struct pci_config_table *);
567 unsigned long priv[3];
568};
569
Wolfgang Denk993a2272006-03-12 16:54:11 +0100570extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
571 struct pci_config_table *);
wdenkc6097192002-11-03 00:24:07 +0000572extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
573 struct pci_config_table *);
574
Simon Glass62c72992019-05-07 21:41:15 -0600575#define MAX_PCI_REGIONS 7
wdenkc6097192002-11-03 00:24:07 +0000576
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300577#define INDIRECT_TYPE_NO_PCIE_LINK 1
578
Simon Glass2206ac22019-12-06 21:41:37 -0700579/**
wdenkc6097192002-11-03 00:24:07 +0000580 * Structure of a PCI controller (host bridge)
Simon Glass54fe7b12015-11-26 19:51:21 -0700581 *
582 * With driver model this is dev_get_uclass_priv(bus)
Simon Glass2206ac22019-12-06 21:41:37 -0700583 *
584 * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has
585 * relocated. Normally if PCI is used before relocation, this happens
586 * before relocation also. Some platforms set up static configuration in
587 * TPL/SPL to reduce code size and boot time, since these phases only know
588 * about a small subset of PCI devices. This is normally false.
wdenkc6097192002-11-03 00:24:07 +0000589 */
590struct pci_controller {
Simon Glassff3e0772015-03-05 12:25:25 -0700591#ifdef CONFIG_DM_PCI
592 struct udevice *bus;
593 struct udevice *ctlr;
Simon Glass2206ac22019-12-06 21:41:37 -0700594 bool skip_auto_config_until_reloc;
Simon Glassff3e0772015-03-05 12:25:25 -0700595#else
wdenkc6097192002-11-03 00:24:07 +0000596 struct pci_controller *next;
Simon Glassff3e0772015-03-05 12:25:25 -0700597#endif
wdenkc6097192002-11-03 00:24:07 +0000598
599 int first_busno;
600 int last_busno;
601
602 volatile unsigned int *cfg_addr;
603 volatile unsigned char *cfg_data;
604
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300605 int indirect_type;
606
Simon Glassaec241d2015-06-07 08:50:40 -0600607 /*
608 * TODO(sjg@chromium.org): With driver model we use struct
609 * pci_controller for both the controller and any bridge devices
610 * attached to it. But there is only one region list and it is in the
611 * top-level controller.
612 *
613 * This could be changed so that struct pci_controller is only used
614 * for PCI controllers and a separate UCLASS (or perhaps
615 * UCLASS_PCI_GENERIC) is used for bridges.
616 */
wdenkc6097192002-11-03 00:24:07 +0000617 struct pci_region regions[MAX_PCI_REGIONS];
618 int region_count;
619
620 struct pci_config_table *config_table;
621
622 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
Simon Glassff3e0772015-03-05 12:25:25 -0700623#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000624 /* Low-level architecture-dependent routines */
625 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
626 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
627 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
628 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
629 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
630 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
Simon Glassff3e0772015-03-05 12:25:25 -0700631#endif
wdenkc6097192002-11-03 00:24:07 +0000632
633 /* Used by auto config */
Kumar Galaa1790122006-01-11 13:24:15 -0600634 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000635
Simon Glassff3e0772015-03-05 12:25:25 -0700636#ifndef CONFIG_DM_PCI
wdenkc7de8292002-11-19 11:04:11 +0000637 int current_busno;
Leo Liu10fa8d72011-01-19 19:50:47 +0800638
639 void *priv_data;
Simon Glassff3e0772015-03-05 12:25:25 -0700640#endif
wdenkc6097192002-11-03 00:24:07 +0000641};
642
Simon Glassff3e0772015-03-05 12:25:25 -0700643#ifndef CONFIG_DM_PCI
Simon Glassbc3442a2013-06-11 11:14:33 -0700644static inline void pci_set_ops(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000645 int (*read_byte)(struct pci_controller*,
646 pci_dev_t, int where, u8 *),
647 int (*read_word)(struct pci_controller*,
648 pci_dev_t, int where, u16 *),
649 int (*read_dword)(struct pci_controller*,
650 pci_dev_t, int where, u32 *),
651 int (*write_byte)(struct pci_controller*,
652 pci_dev_t, int where, u8),
653 int (*write_word)(struct pci_controller*,
654 pci_dev_t, int where, u16),
655 int (*write_dword)(struct pci_controller*,
656 pci_dev_t, int where, u32)) {
657 hose->read_byte = read_byte;
658 hose->read_word = read_word;
659 hose->read_dword = read_dword;
660 hose->write_byte = write_byte;
661 hose->write_word = write_word;
662 hose->write_dword = write_dword;
663}
Simon Glassff3e0772015-03-05 12:25:25 -0700664#endif
wdenkc6097192002-11-03 00:24:07 +0000665
Gabor Juhos842033e2013-05-30 07:06:12 +0000666#ifdef CONFIG_PCI_INDIRECT_BRIDGE
wdenkc6097192002-11-03 00:24:07 +0000667extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
Gabor Juhos842033e2013-05-30 07:06:12 +0000668#endif
wdenkc6097192002-11-03 00:24:07 +0000669
Simon Glass7e78b9e2015-11-29 13:18:05 -0700670#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Becky Bruce36f32672008-05-07 13:24:57 -0500671extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
Kumar Gala30e76d52008-10-21 08:36:08 -0500672 pci_addr_t addr, unsigned long flags);
673extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
674 phys_addr_t addr, unsigned long flags);
wdenkc6097192002-11-03 00:24:07 +0000675
676#define pci_phys_to_bus(dev, addr, flags) \
677 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
678#define pci_bus_to_phys(dev, addr, flags) \
679 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
680
Becky Bruce6e61fae2009-02-03 18:10:50 -0600681#define pci_virt_to_bus(dev, addr, flags) \
682 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
683 (virt_to_phys(addr)), (flags))
684#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
685 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
686 (addr), (flags)), \
687 (len), (map_flags))
688
689#define pci_phys_to_mem(dev, addr) \
690 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
691#define pci_mem_to_phys(dev, addr) \
692 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
693#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
694#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
695
696#define pci_virt_to_mem(dev, addr) \
697 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
698#define pci_mem_to_virt(dev, addr, len, map_flags) \
699 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
700#define pci_virt_to_io(dev, addr) \
701 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
702#define pci_io_to_virt(dev, addr, len, map_flags) \
703 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
wdenkc6097192002-11-03 00:24:07 +0000704
Simon Glassdc5740d2015-08-22 15:58:55 -0600705/* For driver model these are defined in macros in pci_compat.c */
wdenkc6097192002-11-03 00:24:07 +0000706extern int pci_hose_read_config_byte(struct pci_controller *hose,
707 pci_dev_t dev, int where, u8 *val);
708extern int pci_hose_read_config_word(struct pci_controller *hose,
709 pci_dev_t dev, int where, u16 *val);
710extern int pci_hose_read_config_dword(struct pci_controller *hose,
711 pci_dev_t dev, int where, u32 *val);
712extern int pci_hose_write_config_byte(struct pci_controller *hose,
713 pci_dev_t dev, int where, u8 val);
714extern int pci_hose_write_config_word(struct pci_controller *hose,
715 pci_dev_t dev, int where, u16 val);
716extern int pci_hose_write_config_dword(struct pci_controller *hose,
717 pci_dev_t dev, int where, u32 val);
Simon Glass3ba5f742015-11-26 19:51:30 -0700718#endif
wdenkc6097192002-11-03 00:24:07 +0000719
Simon Glassff3e0772015-03-05 12:25:25 -0700720#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000721extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
722extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
723extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
724extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
725extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
726extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
Simon Glassff3e0772015-03-05 12:25:25 -0700727#endif
wdenkc6097192002-11-03 00:24:07 +0000728
Simon Glass3ba5f742015-11-26 19:51:30 -0700729void pciauto_region_init(struct pci_region *res);
730void pciauto_region_align(struct pci_region *res, pci_size_t size);
731void pciauto_config_init(struct pci_controller *hose);
Tuomas Tynkkynen5ce9aca2018-05-14 23:50:05 +0300732
733/**
734 * pciauto_region_allocate() - Allocate resources from a PCI resource region
735 *
736 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
737 * false, the result will be guaranteed to fit in 32 bits.
738 *
739 * @res: PCI region to allocate from
740 * @size: Amount of bytes to allocate
741 * @bar: Returns the PCI bus address of the allocated resource
742 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
743 * @return 0 if successful, -1 on failure
744 */
Simon Glass3ba5f742015-11-26 19:51:30 -0700745int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
Tuomas Tynkkynend71975a2018-05-14 19:38:13 +0300746 pci_addr_t *bar, bool supports_64bit);
Simon Glass3ba5f742015-11-26 19:51:30 -0700747
748#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
wdenkc6097192002-11-03 00:24:07 +0000749extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
750 pci_dev_t dev, int where, u8 *val);
751extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
752 pci_dev_t dev, int where, u16 *val);
753extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
754 pci_dev_t dev, int where, u8 val);
755extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
756 pci_dev_t dev, int where, u16 val);
757
Becky Bruce6e61fae2009-02-03 18:10:50 -0600758extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
wdenkc6097192002-11-03 00:24:07 +0000759extern void pci_register_hose(struct pci_controller* hose);
760extern struct pci_controller* pci_bus_to_hose(int bus);
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600761extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
Stuart Yodereeb5b1a2016-03-10 10:52:18 -0600762extern struct pci_controller *pci_get_hose_head(void);
wdenkc6097192002-11-03 00:24:07 +0000763
Thierry Reding4efe52b2014-11-12 18:26:49 -0700764extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000765extern int pci_hose_scan(struct pci_controller *hose);
766extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
767
wdenkc6097192002-11-03 00:24:07 +0000768extern void pciauto_setup_device(struct pci_controller *hose,
769 pci_dev_t dev, int bars_num,
770 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -0600771 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +0000772 struct pci_region *io);
Linus Walleija3a70722012-03-25 12:13:15 +0000773extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
774 pci_dev_t dev, int sub_bus);
775extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
776 pci_dev_t dev, int sub_bus);
Linus Walleija3a70722012-03-25 12:13:15 +0000777extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000778
779extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
780extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
Simon Glass250e0392015-01-27 22:13:27 -0700781pci_dev_t pci_find_class(unsigned int find_class, int index);
wdenkc6097192002-11-03 00:24:07 +0000782
Zhao Qiang287df012013-10-12 13:46:33 +0800783extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
784 int cap);
785extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
786 u8 hdr_type);
787extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
788 int cap);
789
Minghuan Lianed5b5802015-07-10 11:35:08 +0800790int pci_find_next_ext_capability(struct pci_controller *hose,
791 pci_dev_t dev, int start, int cap);
792int pci_hose_find_ext_capability(struct pci_controller *hose,
793 pci_dev_t dev, int cap);
794
Tim Harvey09918662014-08-07 22:49:56 -0700795#ifdef CONFIG_PCI_FIXUP_DEV
796extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
797 unsigned short vendor,
798 unsigned short device,
799 unsigned short class);
800#endif
Simon Glass3ba5f742015-11-26 19:51:30 -0700801#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
Tim Harvey09918662014-08-07 22:49:56 -0700802
Peter Tyser983eb9d2010-10-29 17:59:27 -0500803const char * pci_class_str(u8 class);
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300804int pci_last_busno(void);
805
Jon Loeliger13a7fcd2006-10-19 11:33:52 -0500806#ifdef CONFIG_MPC85xx
807extern void pci_mpc85xx_init (struct pci_controller *hose);
808#endif
Paul Burtonfa5cec02013-11-08 11:18:47 +0000809
Tim Harvey6ecbe132017-05-12 12:58:41 -0700810#ifdef CONFIG_PCIE_IMX
811extern void imx_pcie_remove(void);
812#endif
813
Simon Glass3ba5f742015-11-26 19:51:30 -0700814#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Simon Glasse8a552e2014-11-14 18:18:30 -0700815/**
816 * pci_write_bar32() - Write the address of a BAR including control bits
817 *
Simon Glass9d731c82016-01-18 20:19:15 -0700818 * This writes a raw address (with control bits) to a bar. This can be used
819 * with devices which require hard-coded addresses, not part of the normal
820 * PCI enumeration process.
Simon Glasse8a552e2014-11-14 18:18:30 -0700821 *
822 * @hose: PCI hose to use
823 * @dev: PCI device to update
824 * @barnum: BAR number (0-5)
825 * @addr: BAR address with control bits
826 */
827void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
Simon Glass9d731c82016-01-18 20:19:15 -0700828 u32 addr);
Simon Glasse8a552e2014-11-14 18:18:30 -0700829
830/**
831 * pci_read_bar32() - read the address of a bar
832 *
833 * @hose: PCI hose to use
834 * @dev: PCI device to inspect
835 * @barnum: BAR number (0-5)
836 * @return address of the bar, masking out any control bits
837 * */
838u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
839
Simon Glass4a2708a2015-01-14 21:37:04 -0700840/**
Simon Glassaab67242015-03-05 12:25:24 -0700841 * pci_hose_find_devices() - Find devices by vendor/device ID
842 *
843 * @hose: PCI hose to search
844 * @busnum: Bus number to search
845 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
846 * @indexp: Pointer to device index to find. To find the first matching
847 * device, pass 0; to find the second, pass 1, etc. This
848 * parameter is decremented for each non-matching device so
849 * can be called repeatedly.
850 */
851pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
852 struct pci_device_id *ids, int *indexp);
Simon Glass3ba5f742015-11-26 19:51:30 -0700853#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
Simon Glassaab67242015-03-05 12:25:24 -0700854
Simon Glassff3e0772015-03-05 12:25:25 -0700855/* Access sizes for PCI reads and writes */
856enum pci_size_t {
857 PCI_SIZE_8,
858 PCI_SIZE_16,
859 PCI_SIZE_32,
860};
861
862struct udevice;
863
864#ifdef CONFIG_DM_PCI
865/**
866 * struct pci_child_platdata - information stored about each PCI device
867 *
868 * Every device on a PCI bus has this per-child data.
869 *
Simon Glass7d38db52019-02-16 20:24:41 -0700870 * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
Simon Glassff3e0772015-03-05 12:25:25 -0700871 * PCI bus (i.e. UCLASS_PCI)
872 *
873 * @devfn: Encoded device and function index - see PCI_DEVFN()
874 * @vendor: PCI vendor ID (see pci_ids.h)
875 * @device: PCI device ID (see pci_ids.h)
876 * @class: PCI class, 3 bytes: (base, sub, prog-if)
877 */
878struct pci_child_platdata {
879 int devfn;
880 unsigned short vendor;
881 unsigned short device;
882 unsigned int class;
883};
884
885/* PCI bus operations */
886struct dm_pci_ops {
887 /**
888 * read_config() - Read a PCI configuration value
889 *
890 * PCI buses must support reading and writing configuration values
891 * so that the bus can be scanned and its devices configured.
892 *
893 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
894 * If bridges exist it is possible to use the top-level bus to
895 * access a sub-bus. In that case @bus will be the top-level bus
896 * and PCI_BUS(bdf) will be a different (higher) value
897 *
898 * @bus: Bus to read from
899 * @bdf: Bus, device and function to read
900 * @offset: Byte offset within the device's configuration space
901 * @valuep: Place to put the returned value
902 * @size: Access size
903 * @return 0 if OK, -ve on error
904 */
Simon Glassc4e72c42020-01-27 08:49:37 -0700905 int (*read_config)(const struct udevice *bus, pci_dev_t bdf,
906 uint offset, ulong *valuep, enum pci_size_t size);
Simon Glassff3e0772015-03-05 12:25:25 -0700907 /**
908 * write_config() - Write a PCI configuration value
909 *
910 * @bus: Bus to write to
911 * @bdf: Bus, device and function to write
912 * @offset: Byte offset within the device's configuration space
913 * @value: Value to write
914 * @size: Access size
915 * @return 0 if OK, -ve on error
916 */
917 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
918 ulong value, enum pci_size_t size);
919};
920
921/* Get access to a PCI bus' operations */
922#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
923
924/**
Simon Glass21ccce12015-11-29 13:17:47 -0700925 * dm_pci_get_bdf() - Get the BDF value for a device
Simon Glass4b515e42015-07-06 16:47:46 -0600926 *
927 * @dev: Device to check
928 * @return bus/device/function value (see PCI_BDF())
929 */
Simon Glass194fca92020-01-27 08:49:38 -0700930pci_dev_t dm_pci_get_bdf(const struct udevice *dev);
Simon Glass4b515e42015-07-06 16:47:46 -0600931
932/**
Simon Glassff3e0772015-03-05 12:25:25 -0700933 * pci_bind_bus_devices() - scan a PCI bus and bind devices
934 *
935 * Scan a PCI bus looking for devices. Bind each one that is found. If
936 * devices are already bound that match the scanned devices, just update the
937 * child data so that the device can be used correctly (this happens when
938 * the device tree describes devices we expect to see on the bus).
939 *
940 * Devices that are bound in this way will use a generic PCI driver which
941 * does nothing. The device can still be accessed but will not provide any
942 * driver interface.
943 *
944 * @bus: Bus containing devices to bind
945 * @return 0 if OK, -ve on error
946 */
947int pci_bind_bus_devices(struct udevice *bus);
948
949/**
950 * pci_auto_config_devices() - configure bus devices ready for use
951 *
952 * This works through all devices on a bus by scanning the driver model
953 * data structures (normally these have been set up by pci_bind_bus_devices()
954 * earlier).
955 *
956 * Space is allocated for each PCI base address register (BAR) so that the
957 * devices are mapped into memory and I/O space ready for use.
958 *
959 * @bus: Bus containing devices to bind
960 * @return 0 if OK, -ve on error
961 */
962int pci_auto_config_devices(struct udevice *bus);
963
964/**
Simon Glassf3f1fae2015-11-29 13:17:48 -0700965 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
Simon Glassff3e0772015-03-05 12:25:25 -0700966 *
967 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
968 * @devp: Returns the device for this address, if found
969 * @return 0 if OK, -ENODEV if not found
970 */
Simon Glassf3f1fae2015-11-29 13:17:48 -0700971int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
Simon Glassff3e0772015-03-05 12:25:25 -0700972
973/**
974 * pci_bus_find_devfn() - Find a device on a bus
975 *
976 * @find_devfn: PCI device address (device and function only)
977 * @devp: Returns the device for this address, if found
978 * @return 0 if OK, -ENODEV if not found
979 */
Simon Glassc4e72c42020-01-27 08:49:37 -0700980int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
Simon Glassff3e0772015-03-05 12:25:25 -0700981 struct udevice **devp);
982
983/**
Simon Glass76c3fbc2015-08-10 07:05:04 -0600984 * pci_find_first_device() - return the first available PCI device
985 *
986 * This function and pci_find_first_device() allow iteration through all
987 * available PCI devices on all buses. Assuming there are any, this will
988 * return the first one.
989 *
990 * @devp: Set to the first available device, or NULL if no more are left
991 * or we got an error
992 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
993 */
994int pci_find_first_device(struct udevice **devp);
995
996/**
997 * pci_find_next_device() - return the next available PCI device
998 *
999 * Finds the next available PCI device after the one supplied, or sets @devp
1000 * to NULL if there are no more.
1001 *
1002 * @devp: On entry, the last device returned. Set to the next available
1003 * device, or NULL if no more are left or we got an error
1004 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
1005 */
1006int pci_find_next_device(struct udevice **devp);
1007
1008/**
Simon Glassff3e0772015-03-05 12:25:25 -07001009 * pci_get_ff() - Returns a mask for the given access size
1010 *
1011 * @size: Access size
1012 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
1013 * PCI_SIZE_32
1014 */
1015int pci_get_ff(enum pci_size_t size);
1016
1017/**
1018 * pci_bus_find_devices () - Find devices on a bus
1019 *
1020 * @bus: Bus to search
1021 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1022 * @indexp: Pointer to device index to find. To find the first matching
1023 * device, pass 0; to find the second, pass 1, etc. This
1024 * parameter is decremented for each non-matching device so
1025 * can be called repeatedly.
1026 * @devp: Returns matching device if found
1027 * @return 0 if found, -ENODEV if not
1028 */
1029int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
1030 int *indexp, struct udevice **devp);
1031
1032/**
1033 * pci_find_device_id() - Find a device on any bus
1034 *
1035 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1036 * @index: Index number of device to find, 0 for the first match, 1 for
1037 * the second, etc.
1038 * @devp: Returns matching device if found
1039 * @return 0 if found, -ENODEV if not
1040 */
1041int pci_find_device_id(struct pci_device_id *ids, int index,
1042 struct udevice **devp);
1043
1044/**
1045 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1046 *
1047 * This probes the given bus which causes it to be scanned for devices. The
1048 * devices will be bound but not probed.
1049 *
1050 * @hose specifies the PCI hose that will be used for the scan. This is
1051 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1052 * in @bdf, and is a subordinate bus reachable from @hose.
1053 *
1054 * @hose: PCI hose to scan
1055 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1056 * @return 0 if OK, -ve on error
1057 */
Simon Glass5e23b8b2015-11-29 13:17:49 -07001058int dm_pci_hose_probe_bus(struct udevice *bus);
Simon Glassff3e0772015-03-05 12:25:25 -07001059
1060/**
1061 * pci_bus_read_config() - Read a configuration value from a device
1062 *
1063 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1064 * it do the right thing. It would be good to have that function also.
1065 *
1066 * @bus: Bus to read from
1067 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001068 * @offset: Register offset to read
Simon Glassff3e0772015-03-05 12:25:25 -07001069 * @valuep: Place to put the returned value
1070 * @size: Access size
1071 * @return 0 if OK, -ve on error
1072 */
Simon Glass194fca92020-01-27 08:49:38 -07001073int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
Simon Glassff3e0772015-03-05 12:25:25 -07001074 unsigned long *valuep, enum pci_size_t size);
1075
1076/**
1077 * pci_bus_write_config() - Write a configuration value to a device
1078 *
1079 * @bus: Bus to write from
1080 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001081 * @offset: Register offset to write
Simon Glassff3e0772015-03-05 12:25:25 -07001082 * @value: Value to write
1083 * @size: Access size
1084 * @return 0 if OK, -ve on error
1085 */
1086int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1087 unsigned long value, enum pci_size_t size);
1088
Simon Glass66afb4e2015-08-10 07:05:03 -06001089/**
Simon Glass319dba12016-03-06 19:27:52 -07001090 * pci_bus_clrset_config32() - Update a configuration value for a device
1091 *
1092 * The register at @offset is updated to (oldvalue & ~clr) | set.
1093 *
1094 * @bus: Bus to access
1095 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1096 * @offset: Register offset to update
1097 * @clr: Bits to clear
1098 * @set: Bits to set
1099 * @return 0 if OK, -ve on error
1100 */
1101int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1102 u32 clr, u32 set);
1103
1104/**
Simon Glass66afb4e2015-08-10 07:05:03 -06001105 * Driver model PCI config access functions. Use these in preference to others
1106 * when you have a valid device
1107 */
Simon Glass194fca92020-01-27 08:49:38 -07001108int dm_pci_read_config(const struct udevice *dev, int offset,
1109 unsigned long *valuep, enum pci_size_t size);
Simon Glass66afb4e2015-08-10 07:05:03 -06001110
Simon Glass194fca92020-01-27 08:49:38 -07001111int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep);
1112int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep);
1113int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep);
Simon Glass66afb4e2015-08-10 07:05:03 -06001114
1115int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1116 enum pci_size_t size);
1117
1118int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1119int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1120int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1121
Simon Glass319dba12016-03-06 19:27:52 -07001122/**
1123 * These permit convenient read/modify/write on PCI configuration. The
1124 * register is updated to (oldvalue & ~clr) | set.
1125 */
1126int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1127int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1128int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1129
Simon Glassff3e0772015-03-05 12:25:25 -07001130/*
1131 * The following functions provide access to the above without needing the
1132 * size parameter. We are trying to encourage the use of the 8/16/32-style
1133 * functions, rather than byte/word/dword. But both are supported.
1134 */
1135int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
Bin Meng308143e2016-02-02 05:58:07 -08001136int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1137int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1138int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1139int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1140int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
Simon Glassff3e0772015-03-05 12:25:25 -07001141
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001142/**
1143 * pci_generic_mmap_write_config() - Generic helper for writing to
1144 * memory-mapped PCI configuration space.
1145 * @bus: Pointer to the PCI bus
1146 * @addr_f: Callback for calculating the config space address
1147 * @bdf: Identifies the PCI device to access
1148 * @offset: The offset into the device's configuration space
1149 * @value: The value to write
1150 * @size: Indicates the size of access to perform
1151 *
1152 * Write the value @value of size @size from offset @offset within the
1153 * configuration space of the device identified by the bus, device & function
1154 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1155 * responsible for calculating the CPU address of the respective configuration
1156 * space offset.
1157 *
1158 * Return: 0 on success, else -EINVAL
1159 */
1160int pci_generic_mmap_write_config(
Simon Glassc4e72c42020-01-27 08:49:37 -07001161 const struct udevice *bus,
1162 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1163 void **addrp),
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001164 pci_dev_t bdf,
1165 uint offset,
1166 ulong value,
1167 enum pci_size_t size);
1168
1169/**
1170 * pci_generic_mmap_read_config() - Generic helper for reading from
1171 * memory-mapped PCI configuration space.
1172 * @bus: Pointer to the PCI bus
1173 * @addr_f: Callback for calculating the config space address
1174 * @bdf: Identifies the PCI device to access
1175 * @offset: The offset into the device's configuration space
1176 * @valuep: A pointer at which to store the read value
1177 * @size: Indicates the size of access to perform
1178 *
1179 * Read a value of size @size from offset @offset within the configuration
1180 * space of the device identified by the bus, device & function numbers in @bdf
1181 * on the PCI bus @bus. The callback function @addr_f is responsible for
1182 * calculating the CPU address of the respective configuration space offset.
1183 *
1184 * Return: 0 on success, else -EINVAL
1185 */
1186int pci_generic_mmap_read_config(
Simon Glassc4e72c42020-01-27 08:49:37 -07001187 const struct udevice *bus,
1188 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1189 void **addrp),
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001190 pci_dev_t bdf,
1191 uint offset,
1192 ulong *valuep,
1193 enum pci_size_t size);
1194
Simon Glass3ba5f742015-11-26 19:51:30 -07001195#ifdef CONFIG_DM_PCI_COMPAT
Simon Glassff3e0772015-03-05 12:25:25 -07001196/* Compatibility with old naming */
1197static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1198 u32 value)
1199{
1200 return pci_write_config32(pcidev, offset, value);
1201}
1202
Simon Glassff3e0772015-03-05 12:25:25 -07001203/* Compatibility with old naming */
1204static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1205 u16 value)
1206{
1207 return pci_write_config16(pcidev, offset, value);
1208}
1209
Simon Glassff3e0772015-03-05 12:25:25 -07001210/* Compatibility with old naming */
1211static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1212 u8 value)
1213{
1214 return pci_write_config8(pcidev, offset, value);
1215}
1216
Simon Glassff3e0772015-03-05 12:25:25 -07001217/* Compatibility with old naming */
1218static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1219 u32 *valuep)
1220{
1221 return pci_read_config32(pcidev, offset, valuep);
1222}
1223
Simon Glassff3e0772015-03-05 12:25:25 -07001224/* Compatibility with old naming */
1225static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1226 u16 *valuep)
1227{
1228 return pci_read_config16(pcidev, offset, valuep);
1229}
1230
Simon Glassff3e0772015-03-05 12:25:25 -07001231/* Compatibility with old naming */
1232static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1233 u8 *valuep)
1234{
1235 return pci_read_config8(pcidev, offset, valuep);
1236}
Simon Glass3ba5f742015-11-26 19:51:30 -07001237#endif /* CONFIG_DM_PCI_COMPAT */
1238
1239/**
1240 * dm_pciauto_config_device() - configure a device ready for use
1241 *
1242 * Space is allocated for each PCI base address register (BAR) so that the
1243 * devices are mapped into memory and I/O space ready for use.
1244 *
1245 * @dev: Device to configure
1246 * @return 0 if OK, -ve on error
1247 */
1248int dm_pciauto_config_device(struct udevice *dev);
1249
Simon Glass36d0d3b2015-03-05 12:25:28 -07001250/**
Simon Glass9289db62015-11-19 20:26:59 -07001251 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1252 *
1253 * Some PCI buses must always perform 32-bit reads. The data must then be
1254 * shifted and masked to reflect the required access size and offset. This
1255 * function performs this transformation.
1256 *
1257 * @value: Value to transform (32-bit value read from @offset & ~3)
1258 * @offset: Register offset that was read
1259 * @size: Required size of the result
1260 * @return the value that would have been obtained if the read had been
1261 * performed at the given offset with the correct size
1262 */
1263ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1264
1265/**
1266 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1267 *
1268 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1269 * write the old 32-bit data must be read, updated with the required new data
1270 * and written back as a 32-bit value. This function performs the
1271 * transformation from the old value to the new value.
1272 *
1273 * @value: Value to transform (32-bit value read from @offset & ~3)
1274 * @offset: Register offset that should be written
1275 * @size: Required size of the write
1276 * @return the value that should be written as a 32-bit access to @offset & ~3.
1277 */
1278ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1279 enum pci_size_t size);
1280
1281/**
Simon Glass9f60fb02015-11-19 20:27:00 -07001282 * pci_get_controller() - obtain the controller to use for a bus
1283 *
1284 * @dev: Device to check
1285 * @return pointer to the controller device for this bus
1286 */
1287struct udevice *pci_get_controller(struct udevice *dev);
1288
1289/**
Simon Glassf9260332015-11-19 20:27:01 -07001290 * pci_get_regions() - obtain pointers to all the region types
1291 *
1292 * @dev: Device to check
1293 * @iop: Returns a pointer to the I/O region, or NULL if none
1294 * @memp: Returns a pointer to the memory region, or NULL if none
1295 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1296 * @return the number of non-NULL regions returned, normally 3
1297 */
1298int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1299 struct pci_region **memp, struct pci_region **prefp);
1300
1301/**
Simon Glass9d731c82016-01-18 20:19:15 -07001302 * dm_pci_write_bar32() - Write the address of a BAR
1303 *
1304 * This writes a raw address to a bar
1305 *
1306 * @dev: PCI device to update
1307 * @barnum: BAR number (0-5)
1308 * @addr: BAR address
1309 */
1310void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1311
1312/**
Simon Glassbab17cf2015-11-29 13:17:53 -07001313 * dm_pci_read_bar32() - read a base address register from a device
1314 *
1315 * @dev: Device to check
1316 * @barnum: Bar number to read (numbered from 0)
1317 * @return: value of BAR
1318 */
Simon Glass194fca92020-01-27 08:49:38 -07001319u32 dm_pci_read_bar32(const struct udevice *dev, int barnum);
Simon Glassbab17cf2015-11-29 13:17:53 -07001320
1321/**
Simon Glass21d1fe72015-11-29 13:18:03 -07001322 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1323 *
1324 * @dev: Device containing the PCI address
1325 * @addr: PCI address to convert
1326 * @flags: Flags for the region type (PCI_REGION_...)
1327 * @return physical address corresponding to that PCI bus address
1328 */
1329phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1330 unsigned long flags);
1331
1332/**
1333 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1334 *
1335 * @dev: Device containing the bus address
1336 * @addr: Physical address to convert
1337 * @flags: Flags for the region type (PCI_REGION_...)
1338 * @return PCI bus address corresponding to that physical address
1339 */
1340pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1341 unsigned long flags);
1342
1343/**
1344 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1345 *
1346 * Looks up a base address register and finds the physical memory address
Alex Marginean2204bc12019-06-07 11:24:22 +03001347 * that corresponds to it.
1348 * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
1349 * type 1 functions.
Alex Marginean0b143d82019-06-07 11:24:23 +03001350 * Can also be used on type 0 functions that support Enhanced Allocation for
1351 * 32b/64b BARs. Note that duplicate BEI entries are not supported.
Simon Glass21d1fe72015-11-29 13:18:03 -07001352 *
1353 * @dev: Device to check
Alex Marginean2204bc12019-06-07 11:24:22 +03001354 * @bar: Bar register offset (PCI_BASE_ADDRESS_...)
Simon Glass21d1fe72015-11-29 13:18:03 -07001355 * @flags: Flags for the region type (PCI_REGION_...)
Alex Marginean2204bc12019-06-07 11:24:22 +03001356 * @return: pointer to the virtual address to use or 0 on error
Simon Glass21d1fe72015-11-29 13:18:03 -07001357 */
1358void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1359
Bin Mengdac01fd2018-08-03 01:14:52 -07001360/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001361 * dm_pci_find_next_capability() - find a capability starting from an offset
1362 *
1363 * Tell if a device supports a given PCI capability. Returns the
1364 * address of the requested capability structure within the device's
1365 * PCI configuration space or 0 in case the device does not support it.
1366 *
1367 * Possible values for @cap:
1368 *
1369 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1370 * %PCI_CAP_ID_PCIX PCI-X
1371 * %PCI_CAP_ID_EXP PCI Express
1372 * %PCI_CAP_ID_MSIX MSI-X
1373 *
1374 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1375 *
1376 * @dev: PCI device to query
1377 * @start: offset to start from
1378 * @cap: capability code
1379 * @return: capability address or 0 if not supported
1380 */
1381int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1382
1383/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001384 * dm_pci_find_capability() - find a capability
1385 *
1386 * Tell if a device supports a given PCI capability. Returns the
1387 * address of the requested capability structure within the device's
1388 * PCI configuration space or 0 in case the device does not support it.
1389 *
1390 * Possible values for @cap:
1391 *
1392 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1393 * %PCI_CAP_ID_PCIX PCI-X
1394 * %PCI_CAP_ID_EXP PCI Express
1395 * %PCI_CAP_ID_MSIX MSI-X
1396 *
1397 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1398 *
1399 * @dev: PCI device to query
1400 * @cap: capability code
1401 * @return: capability address or 0 if not supported
1402 */
1403int dm_pci_find_capability(struct udevice *dev, int cap);
1404
1405/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001406 * dm_pci_find_next_ext_capability() - find an extended capability
1407 * starting from an offset
1408 *
1409 * Tell if a device supports a given PCI express extended capability.
1410 * Returns the address of the requested extended capability structure
1411 * within the device's PCI configuration space or 0 in case the device
1412 * does not support it.
1413 *
1414 * Possible values for @cap:
1415 *
1416 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1417 * %PCI_EXT_CAP_ID_VC Virtual Channel
1418 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1419 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1420 *
1421 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1422 *
1423 * @dev: PCI device to query
1424 * @start: offset to start from
1425 * @cap: extended capability code
1426 * @return: extended capability address or 0 if not supported
1427 */
1428int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1429
1430/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001431 * dm_pci_find_ext_capability() - find an extended capability
1432 *
1433 * Tell if a device supports a given PCI express extended capability.
1434 * Returns the address of the requested extended capability structure
1435 * within the device's PCI configuration space or 0 in case the device
1436 * does not support it.
1437 *
1438 * Possible values for @cap:
1439 *
1440 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1441 * %PCI_EXT_CAP_ID_VC Virtual Channel
1442 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1443 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1444 *
1445 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1446 *
1447 * @dev: PCI device to query
1448 * @cap: extended capability code
1449 * @return: extended capability address or 0 if not supported
1450 */
1451int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1452
Alex Margineanb8e1f822019-06-07 11:24:25 +03001453/**
1454 * dm_pci_flr() - Perform FLR if the device suppoorts it
1455 *
1456 * @dev: PCI device to reset
1457 * @return: 0 if OK, -ENOENT if FLR is not supported by dev
1458 */
1459int dm_pci_flr(struct udevice *dev);
1460
Simon Glass21d1fe72015-11-29 13:18:03 -07001461#define dm_pci_virt_to_bus(dev, addr, flags) \
1462 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1463#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1464 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1465 (len), (map_flags))
1466
1467#define dm_pci_phys_to_mem(dev, addr) \
1468 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1469#define dm_pci_mem_to_phys(dev, addr) \
1470 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1471#define dm_pci_phys_to_io(dev, addr) \
1472 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1473#define dm_pci_io_to_phys(dev, addr) \
1474 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1475
1476#define dm_pci_virt_to_mem(dev, addr) \
1477 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1478#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1479 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1480#define dm_pci_virt_to_io(dev, addr) \
Simon Glass4974a6f2016-03-06 19:27:53 -07001481 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
Simon Glass21d1fe72015-11-29 13:18:03 -07001482#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
Simon Glass4974a6f2016-03-06 19:27:53 -07001483 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
Simon Glass21d1fe72015-11-29 13:18:03 -07001484
1485/**
Simon Glass5c0bf642015-11-29 13:17:50 -07001486 * dm_pci_find_device() - find a device by vendor/device ID
1487 *
1488 * @vendor: Vendor ID
1489 * @device: Device ID
1490 * @index: 0 to find the first match, 1 for second, etc.
1491 * @devp: Returns pointer to the device, if found
1492 * @return 0 if found, -ve on error
1493 */
1494int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1495 struct udevice **devp);
1496
1497/**
Simon Glassa0eb8352015-11-29 13:17:52 -07001498 * dm_pci_find_class() - find a device by class
1499 *
1500 * @find_class: 3-byte (24-bit) class value to find
1501 * @index: 0 to find the first match, 1 for second, etc.
1502 * @devp: Returns pointer to the device, if found
1503 * @return 0 if found, -ve on error
1504 */
1505int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1506
1507/**
Simon Glass6498fda2019-09-21 14:32:41 -06001508 * struct pci_emul_uc_priv - holds info about an emulator device
1509 *
1510 * There is always at most one emulator per client
1511 *
1512 * @client: Client device if any, else NULL
1513 */
1514struct pci_emul_uc_priv {
1515 struct udevice *client;
1516};
1517
1518/**
Simon Glass36d0d3b2015-03-05 12:25:28 -07001519 * struct dm_pci_emul_ops - PCI device emulator operations
1520 */
1521struct dm_pci_emul_ops {
1522 /**
Simon Glass36d0d3b2015-03-05 12:25:28 -07001523 * read_config() - Read a PCI configuration value
1524 *
1525 * @dev: Emulated device to read from
1526 * @offset: Byte offset within the device's configuration space
1527 * @valuep: Place to put the returned value
1528 * @size: Access size
1529 * @return 0 if OK, -ve on error
1530 */
Simon Glassc4e72c42020-01-27 08:49:37 -07001531 int (*read_config)(const struct udevice *dev, uint offset,
1532 ulong *valuep, enum pci_size_t size);
Simon Glass36d0d3b2015-03-05 12:25:28 -07001533 /**
1534 * write_config() - Write a PCI configuration value
1535 *
1536 * @dev: Emulated device to write to
1537 * @offset: Byte offset within the device's configuration space
1538 * @value: Value to write
1539 * @size: Access size
1540 * @return 0 if OK, -ve on error
1541 */
1542 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1543 enum pci_size_t size);
1544 /**
1545 * read_io() - Read a PCI I/O value
1546 *
1547 * @dev: Emulated device to read from
1548 * @addr: I/O address to read
1549 * @valuep: Place to put the returned value
1550 * @size: Access size
1551 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1552 * other -ve value on error
1553 */
1554 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1555 enum pci_size_t size);
1556 /**
1557 * write_io() - Write a PCI I/O value
1558 *
1559 * @dev: Emulated device to write from
1560 * @addr: I/O address to write
1561 * @value: Value to write
1562 * @size: Access size
1563 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1564 * other -ve value on error
1565 */
1566 int (*write_io)(struct udevice *dev, unsigned int addr,
1567 ulong value, enum pci_size_t size);
1568 /**
1569 * map_physmem() - Map a device into sandbox memory
1570 *
1571 * @dev: Emulated device to map
1572 * @addr: Memory address, normally corresponding to a PCI BAR.
1573 * The device should have been configured to have a BAR
1574 * at this address.
1575 * @lenp: On entry, the size of the area to map, On exit it is
1576 * updated to the size actually mapped, which may be less
1577 * if the device has less space
1578 * @ptrp: Returns a pointer to the mapped address. The device's
1579 * space can be accessed as @lenp bytes starting here
1580 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1581 * other -ve value on error
1582 */
1583 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1584 unsigned long *lenp, void **ptrp);
1585 /**
1586 * unmap_physmem() - undo a memory mapping
1587 *
1588 * This must be called after map_physmem() to undo the mapping.
1589 * Some devices can use this to check what has been written into
1590 * their mapped memory and perform an operations they require on it.
1591 * In this way, map/unmap can be used as a sort of handshake between
1592 * the emulated device and its users.
1593 *
1594 * @dev: Emuated device to unmap
1595 * @vaddr: Mapped memory address, as passed to map_physmem()
1596 * @len: Size of area mapped, as returned by map_physmem()
1597 * @return 0 if OK, -ve on error
1598 */
1599 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1600 unsigned long len);
1601};
1602
1603/* Get access to a PCI device emulator's operations */
1604#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1605
1606/**
1607 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1608 *
1609 * Searches for a suitable emulator for the given PCI bus device
1610 *
1611 * @bus: PCI bus to search
1612 * @find_devfn: PCI device and function address (PCI_DEVFN())
Bin Meng43459982018-08-03 01:14:45 -07001613 * @containerp: Returns container device if found
Simon Glass36d0d3b2015-03-05 12:25:28 -07001614 * @emulp: Returns emulated device if found
1615 * @return 0 if found, -ENODEV if not found
1616 */
Simon Glassc4e72c42020-01-27 08:49:37 -07001617int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn,
Bin Meng43459982018-08-03 01:14:45 -07001618 struct udevice **containerp, struct udevice **emulp);
Simon Glass36d0d3b2015-03-05 12:25:28 -07001619
Stefan Roeseb5214202019-01-25 11:52:42 +01001620/**
Simon Glass6498fda2019-09-21 14:32:41 -06001621 * sandbox_pci_get_client() - Find the client for an emulation device
1622 *
1623 * @emul: Emulation device to check
1624 * @devp: Returns the client device emulated by this device
1625 * @return 0 if OK, -ENOENT if the device has no client yet
1626 */
1627int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
1628
Simon Glassaba92962015-07-06 16:47:44 -06001629#endif /* CONFIG_DM_PCI */
1630
1631/**
1632 * PCI_DEVICE - macro used to describe a specific pci device
1633 * @vend: the 16 bit PCI Vendor ID
1634 * @dev: the 16 bit PCI Device ID
1635 *
1636 * This macro is used to create a struct pci_device_id that matches a
1637 * specific device. The subvendor and subdevice fields will be set to
1638 * PCI_ANY_ID.
1639 */
1640#define PCI_DEVICE(vend, dev) \
1641 .vendor = (vend), .device = (dev), \
1642 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1643
1644/**
1645 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1646 * @vend: the 16 bit PCI Vendor ID
1647 * @dev: the 16 bit PCI Device ID
1648 * @subvend: the 16 bit PCI Subvendor ID
1649 * @subdev: the 16 bit PCI Subdevice ID
1650 *
1651 * This macro is used to create a struct pci_device_id that matches a
1652 * specific device with subsystem information.
1653 */
1654#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1655 .vendor = (vend), .device = (dev), \
1656 .subvendor = (subvend), .subdevice = (subdev)
1657
1658/**
1659 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1660 * @dev_class: the class, subclass, prog-if triple for this device
1661 * @dev_class_mask: the class mask for this device
1662 *
1663 * This macro is used to create a struct pci_device_id that matches a
1664 * specific PCI class. The vendor, device, subvendor, and subdevice
1665 * fields will be set to PCI_ANY_ID.
1666 */
1667#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1668 .class = (dev_class), .class_mask = (dev_class_mask), \
1669 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1670 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1671
1672/**
1673 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1674 * @vend: the vendor name
1675 * @dev: the 16 bit PCI Device ID
1676 *
1677 * This macro is used to create a struct pci_device_id that matches a
1678 * specific PCI device. The subvendor, and subdevice fields will be set
1679 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1680 * private data.
1681 */
1682
1683#define PCI_VDEVICE(vend, dev) \
1684 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1685 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1686
1687/**
1688 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1689 * @driver: Driver to use
1690 * @match: List of match records for this driver, terminated by {}
1691 */
1692struct pci_driver_entry {
1693 struct driver *driver;
1694 const struct pci_device_id *match;
1695};
1696
1697#define U_BOOT_PCI_DEVICE(__name, __match) \
1698 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1699 .driver = llsym(struct driver, __name, driver), \
1700 .match = __match, \
1701 }
Simon Glassff3e0772015-03-05 12:25:25 -07001702
Paul Burtonfa5cec02013-11-08 11:18:47 +00001703#endif /* __ASSEMBLY__ */
1704#endif /* _PCI_H */