blob: 8fda3f29fabddb1b0f8af6cfed82e340c6b6d85c [file] [log] [blame]
Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Detlev Zundela99715b2008-04-18 14:50:01 +02002 * (C) Copyright 2007, 2008 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * ADS5121 board configuration file
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Martha Marx16bee7b2008-05-29 15:37:21 -040030#define CONFIG_ADS5121 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +020031/*
32 * Memory map for the ADS5121 board:
33 *
34 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
35 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
36 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
37 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
John Rigby5f91db72008-02-26 09:38:14 -070038 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
39 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
40 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020041 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
42 */
43
44/*
45 * High Level Configuration Options
46 */
47#define CONFIG_E300 1 /* E300 Family */
48#define CONFIG_MPC512X 1 /* MPC512X family */
York Sun0e1bad42008-05-05 10:20:01 -050049#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
John Rigby92c20fb2008-10-30 16:39:35 -060050#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */
York Sun0e1bad42008-05-05 10:20:01 -050051
52/* video */
53#undef CONFIG_VIDEO
54
55#if defined(CONFIG_VIDEO)
56#define CONFIG_CFB_CONSOLE
57#define CONFIG_VGA_AS_SINGLE_DEVICE
58#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020059
John Rigby5f91db72008-02-26 09:38:14 -070060/* CONFIG_PCI is defined at config time */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020061
Martha Marxf31c49d2008-05-29 14:23:25 -040062#ifdef CONFIG_ADS5121_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040064#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040066#define CONFIG_PCI
67#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020068
69#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
York Sun0e1bad42008-05-05 10:20:01 -050070#define CONFIG_MISC_INIT_R
Rafal Jaworowski8993e542007-07-27 14:43:59 +020071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_IMMR 0x80000000
73#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020074
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
76#define CONFIG_SYS_MEMTEST_END 0x00400000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020077
78/*
79 * DDR Setup - manually set all parameters as there's no SPD etc.
80 */
Martha Marxf31c49d2008-05-29 14:23:25 -040081#ifdef CONFIG_ADS5121_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040083#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_DDR_SIZE 512 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040085#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
87#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Rafal Jaworowski8993e542007-07-27 14:43:59 +020088
89/* DDR Controller Configuration
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020090 *
91 * SYS_CFG:
92 * [31:31] MDDRC Soft Reset: Diabled
93 * [30:30] DRAM CKE pin: Enabled
94 * [29:29] DRAM CLK: Enabled
95 * [28:28] Command Mode: Enabled (For initialization only)
96 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
97 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
98 * [20:19] Read Test: DON'T USE
99 * [18:18] Self Refresh: Enabled
100 * [17:17] 16bit Mode: Disabled
101 * [16:13] Ready Delay: 2
102 * [12:12] Half DQS Delay: Disabled
103 * [11:11] Quarter DQS Delay: Disabled
104 * [10:08] Write Delay: 2
105 * [07:07] Early ODT: Disabled
106 * [06:06] On DIE Termination: Disabled
107 * [05:05] FIFO Overflow Clear: DON'T USE here
108 * [04:04] FIFO Underflow Clear: DON'T USE here
109 * [03:03] FIFO Overflow Pending: DON'T USE here
110 * [02:02] FIFO Underlfow Pending: DON'T USE here
111 * [01:01] FIFO Overlfow Enabled: Enabled
112 * [00:00] FIFO Underflow Enabled: Enabled
113 * TIME_CFG0
114 * [31:16] DRAM Refresh Time: 0 CSB clocks
115 * [15:8] DRAM Command Time: 0 CSB clocks
116 * [07:00] DRAM Precharge Time: 0 CSB clocks
117 * TIME_CFG1
118 * [31:26] DRAM tRFC:
119 * [25:21] DRAM tWR1:
120 * [20:17] DRAM tWRT1:
121 * [16:11] DRAM tDRR:
122 * [10:05] DRAM tRC:
123 * [04:00] DRAM tRAS:
124 * TIME_CFG2
125 * [31:28] DRAM tRCD:
126 * [27:23] DRAM tFAW:
127 * [22:19] DRAM tRTW1:
128 * [18:15] DRAM tCCD:
129 * [14:10] DRAM tRTP:
130 * [09:05] DRAM tRP:
131 * [04:00] DRAM tRPA
132 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400133#ifdef CONFIG_ADS5121_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00
135#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00
136#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
137#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
Martha Marxf31c49d2008-05-29 14:23:25 -0400138#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
140#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
141#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
142#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
Martha Marxf31c49d2008-05-29 14:23:25 -0400143#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
145#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
146#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MICRON_NOP 0x01380000
149#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
150#define CONFIG_SYS_MICRON_EM2 0x01020000
151#define CONFIG_SYS_MICRON_EM3 0x01030000
152#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
153#define CONFIG_SYS_MICRON_RFSH 0x01080000
154#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
155#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200156
157/* DDR Priority Manager Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
159#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
160#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
161#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
162#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
163#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
164#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
165#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
166#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
167#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
168#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
169#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
170#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
171#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
172#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
173#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
174#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
175#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
176#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
177#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
178#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
179#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
180#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200181
182/*
183 * NOR FLASH on the Local Bus
184 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400185#undef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200187#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Martha Marxf31c49d2008-05-29 14:23:25 -0400188#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
190#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400191#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
193#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400194#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
196#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
197#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
198#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#undef CONFIG_SYS_FLASH_CHECKSUM
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200201
202/*
203 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
204 * window is 64KB
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_CPLD_BASE 0x82000000
207#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_SRAM_BASE 0x30000000
210#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
213#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
214#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200215
216/* Use SRAM for initial stack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
218#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
225#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
York Sun0e1bad42008-05-05 10:20:01 -0500226#ifdef CONFIG_FSL_DIU_FB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
York Sun0e1bad42008-05-05 10:20:01 -0500228#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
York Sun0e1bad42008-05-05 10:20:01 -0500230#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200231
232/*
233 * Serial Port
234 */
235#define CONFIG_CONS_INDEX 1
236#undef CONFIG_SERIAL_SOFTWARE_FIFO
237
238/*
239 * Serial console configuration
240 */
241#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
242#if CONFIG_PSC_CONSOLE != 3
243#error CONFIG_PSC_CONSOLE must be 3
244#endif
245#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BAUDRATE_TABLE \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
248
249#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
250#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
251#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
252#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
253
254#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
255/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_HUSH_PARSER
257#ifdef CONFIG_SYS_HUSH_PARSER
258#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200259#endif
260
John Rigby5f91db72008-02-26 09:38:14 -0700261/*
262 * PCI
263 */
264#ifdef CONFIG_PCI
265
266/*
267 * General PCI
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
270#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
271#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
272#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
273#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
274#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
275#define CONFIG_SYS_PCI_IO_BASE 0x00000000
276#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
277#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
John Rigby5f91db72008-02-26 09:38:14 -0700278
279
280#define CONFIG_PCI_PNP /* do pci plug-and-play */
281
282#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
283
284#endif
285
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200286/* I2C */
287#define CONFIG_HARD_I2C /* I2C with hardware support */
288#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
289#define CONFIG_I2C_MULTI_BUS
290#define CONFIG_I2C_CMD_TREE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
292#define CONFIG_SYS_I2C_SLAVE 0x7F
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200293#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200295#endif
296
297/*
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700298 * IIM - IC Identification Module
299 */
300#undef CONFIG_IIM
301
302/*
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200303 * EEPROM configuration
304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
306#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
307#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
308#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200309
310/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200311 * Ethernet configuration
312 */
313#define CONFIG_MPC512x_FEC 1
314#define CONFIG_NET_MULTI
315#define CONFIG_PHY_ADDR 0x1
316#define CONFIG_MII 1 /* MII PHY management */
Martha Marxf31c49d2008-05-29 14:23:25 -0400317#define CONFIG_FEC_AN_TIMEOUT 1
John Rigbyef11df62008-08-05 17:38:57 -0600318#define CONFIG_HAS_ETH0
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200319
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200320/*
321 * Configure on-board RTC
322 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400323#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200325
326/*
327 * Environment
328 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200329#define CONFIG_ENV_IS_IN_FLASH 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200330/* This has to be a multiple of the Flash sector size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200332#define CONFIG_ENV_SIZE 0x2000
Martha Marxf31c49d2008-05-29 14:23:25 -0400333#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200334#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400335#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200336#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400337#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200338
339/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200340#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
341#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200342
343#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200345
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200346#include <config_cmd_default.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200347
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200348#define CONFIG_CMD_ASKENV
349#define CONFIG_CMD_DHCP
350#define CONFIG_CMD_I2C
351#define CONFIG_CMD_MII
352#define CONFIG_CMD_NFS
353#define CONFIG_CMD_PING
354#define CONFIG_CMD_REGINFO
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200355#define CONFIG_CMD_EEPROM
Martha Marxf31c49d2008-05-29 14:23:25 -0400356#define CONFIG_CMD_DATE
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700357#undef CONFIG_CMD_FUSE
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700358#define CONFIG_CMD_IDE
359#define CONFIG_CMD_EXT2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200360
361#if defined(CONFIG_PCI)
362#define CONFIG_CMD_PCI
363#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200364
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700365#if defined(CONFIG_CMD_IDE)
366#define CONFIG_DOS_PARTITION
367#define CONFIG_MAC_PARTITION
368#define CONFIG_ISO_PARTITION
369#endif /* defined(CONFIG_CMD_IDE) */
370
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200371/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
373 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200374 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
375 * to chapter 36 of the MPC5121e Reference Manual.
376 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100377/* #define CONFIG_WATCHDOG */ /* enable watchdog */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200379
380 /*
381 * Miscellaneous configurable options
382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_LONGHELP /* undef to save memory */
384#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
385#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200386
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200387#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200389#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200391#endif
392
393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
395#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
396#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
397#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200398
399/*
400 * For booting Linux, the board info and command line data
401 * have to be in the first 8 MB of memory, since this is
402 * the maximum mapped by the Linux kernel during initialization.
403 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200405
406/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_DCACHE_SIZE 32768
408#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200409#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200411#endif
412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_HID0_INIT 0x000000000
414#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
415#define CONFIG_SYS_HID2 HID2_HBE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200416
Becky Bruce31d82672008-05-08 19:02:12 -0500417#define CONFIG_HIGH_BATS 1 /* High BATs supported */
418
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200419/*
420 * Internal Definitions
421 *
422 * Boot Flags
423 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100424#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
425#define BOOTFLAG_WARM 0x02 /* Software reboot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200426
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200427#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200428#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
429#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
430#endif
431
432/*
433 * Environment Configuration
434 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100435#define CONFIG_TIMESTAMP
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200436
437#define CONFIG_HOSTNAME ads5121
Wolfgang Denk8d103072008-01-13 23:37:50 +0100438#define CONFIG_BOOTFILE ads5121/uImage
Wolfgang Denkdd820b02008-09-18 13:57:32 +0200439#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200440
Wolfgang Denk8d103072008-01-13 23:37:50 +0100441#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200442
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200443#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200444#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
445
446#define CONFIG_BAUDRATE 115200
447
448#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100449 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200450 "echo"
451
452#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100453 "u-boot_addr_r=200000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200454 "kernel_addr_r=600000\0" \
455 "fdt_addr_r=880000\0" \
456 "ramdisk_addr_r=900000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100457 "u-boot_addr=FFF00000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200458 "kernel_addr=FFC40000\0" \
459 "fdt_addr=FFEC0000\0" \
460 "ramdisk_addr=FC040000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100461 "ramdiskfile=ads5121/uRamdisk\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100462 "u-boot=ads5121/u-boot.bin\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200463 "bootfile=ads5121/uImage\0" \
464 "fdtfile=ads5121/ads5121.dtb\0" \
465 "rootpath=/opt/eldk/ppc_6xx\n" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200466 "netdev=eth0\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100467 "consdev=ttyPSC0\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200468 "nfsargs=setenv bootargs root=/dev/nfs rw " \
469 "nfsroot=${serverip}:${rootpath}\0" \
470 "ramargs=setenv bootargs root=/dev/ram rw\0" \
471 "addip=setenv bootargs ${bootargs} " \
472 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
473 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100474 "addtty=setenv bootargs ${bootargs} " \
475 "console=${consdev},${baudrate}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200476 "flash_nfs=run nfsargs addip addtty;" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200477 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200478 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100479 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
480 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
481 "tftp ${fdt_addr_r} ${fdtfile};" \
482 "run nfsargs addip addtty;" \
483 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
484 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
485 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200486 "tftp ${fdt_addr_r} ${fdtfile};" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100487 "run ramargs addip addtty;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100488 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
Detlev Zundela99715b2008-04-18 14:50:01 +0200489 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100490 "update=protect off ${u-boot_addr} +${filesize};" \
491 "era ${u-boot_addr} +${filesize};" \
492 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
493 "upd=run load update\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200494 ""
495
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200496#define CONFIG_BOOTCOMMAND "run flash_self"
497
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100498#define CONFIG_OF_LIBFDT 1
499#define CONFIG_OF_BOARD_SETUP 1
John Rigbyef11df62008-08-05 17:38:57 -0600500#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100501
502#define OF_CPU "PowerPC,5121@0"
John Rigbyef11df62008-08-05 17:38:57 -0600503#define OF_SOC_COMPAT "fsl,mpc5121-immr"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100504#define OF_TBCLK (bd->bi_busfreq / 4)
John Rigbyac915282008-01-30 13:36:57 -0700505#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100506
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700507/*-----------------------------------------------------------------------
508 * IDE/ATA stuff
509 *-----------------------------------------------------------------------
510 */
511
512#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
513#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
514#undef CONFIG_IDE_LED /* LED for IDE not supported */
515
516#define CONFIG_IDE_RESET /* reset for IDE supported */
517#define CONFIG_IDE_PREINIT
518
519#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
520#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
521
522#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
523#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA
524
525/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
526#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
527
528/* Offset for normal register accesses */
529#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
530
531/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
532#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
533
534/* Interval between registers */
535#define CONFIG_SYS_ATA_STRIDE 4
536
537#define ATA_BASE_ADDR MPC512X_PATA
538
539/*
540 * Control register bit definitions
541 */
542#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
543#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
544#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
545#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
546#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
547#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
548#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
549#define FSL_ATA_CTRL_IORDY_EN 0x01000000
550
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200551#endif /* __CONFIG_H */