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Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Detlev Zundela99715b2008-04-18 14:50:01 +02002 * (C) Copyright 2007, 2008 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * ADS5121 board configuration file
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Martha Marx16bee7b2008-05-29 15:37:21 -040030#define CONFIG_ADS5121 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +020031/*
32 * Memory map for the ADS5121 board:
33 *
34 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
35 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
36 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
37 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
John Rigby5f91db72008-02-26 09:38:14 -070038 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
39 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
40 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020041 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
42 */
43
44/*
45 * High Level Configuration Options
46 */
47#define CONFIG_E300 1 /* E300 Family */
48#define CONFIG_MPC512X 1 /* MPC512X family */
York Sun0e1bad42008-05-05 10:20:01 -050049#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
50
51/* video */
52#undef CONFIG_VIDEO
53
54#if defined(CONFIG_VIDEO)
55#define CONFIG_CFB_CONSOLE
56#define CONFIG_VGA_AS_SINGLE_DEVICE
57#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020058
John Rigby5f91db72008-02-26 09:38:14 -070059/* CONFIG_PCI is defined at config time */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020060
Martha Marxf31c49d2008-05-29 14:23:25 -040061#ifdef CONFIG_ADS5121_REV2
Rafal Jaworowski8993e542007-07-27 14:43:59 +020062#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040063#else
64#define CFG_MPC512X_CLKIN 33333333 /* in Hz */
65#define CONFIG_PCI
66#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020067
68#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
York Sun0e1bad42008-05-05 10:20:01 -050069#define CONFIG_MISC_INIT_R
Rafal Jaworowski8993e542007-07-27 14:43:59 +020070
71#define CFG_IMMR 0x80000000
York Sun0e1bad42008-05-05 10:20:01 -050072#define CFG_DIU_ADDR (CFG_IMMR+0x2100)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020073
74#define CFG_MEMTEST_START 0x00200000 /* memtest region */
75#define CFG_MEMTEST_END 0x00400000
76
77/*
78 * DDR Setup - manually set all parameters as there's no SPD etc.
79 */
Martha Marxf31c49d2008-05-29 14:23:25 -040080#ifdef CONFIG_ADS5121_REV2
Rafal Jaworowski8993e542007-07-27 14:43:59 +020081#define CFG_DDR_SIZE 256 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040082#else
83#define CFG_DDR_SIZE 512 /* MB */
84#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020085#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
86#define CFG_SDRAM_BASE CFG_DDR_BASE
87
88/* DDR Controller Configuration
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020089 *
90 * SYS_CFG:
91 * [31:31] MDDRC Soft Reset: Diabled
92 * [30:30] DRAM CKE pin: Enabled
93 * [29:29] DRAM CLK: Enabled
94 * [28:28] Command Mode: Enabled (For initialization only)
95 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
96 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
97 * [20:19] Read Test: DON'T USE
98 * [18:18] Self Refresh: Enabled
99 * [17:17] 16bit Mode: Disabled
100 * [16:13] Ready Delay: 2
101 * [12:12] Half DQS Delay: Disabled
102 * [11:11] Quarter DQS Delay: Disabled
103 * [10:08] Write Delay: 2
104 * [07:07] Early ODT: Disabled
105 * [06:06] On DIE Termination: Disabled
106 * [05:05] FIFO Overflow Clear: DON'T USE here
107 * [04:04] FIFO Underflow Clear: DON'T USE here
108 * [03:03] FIFO Overflow Pending: DON'T USE here
109 * [02:02] FIFO Underlfow Pending: DON'T USE here
110 * [01:01] FIFO Overlfow Enabled: Enabled
111 * [00:00] FIFO Underflow Enabled: Enabled
112 * TIME_CFG0
113 * [31:16] DRAM Refresh Time: 0 CSB clocks
114 * [15:8] DRAM Command Time: 0 CSB clocks
115 * [07:00] DRAM Precharge Time: 0 CSB clocks
116 * TIME_CFG1
117 * [31:26] DRAM tRFC:
118 * [25:21] DRAM tWR1:
119 * [20:17] DRAM tWRT1:
120 * [16:11] DRAM tDRR:
121 * [10:05] DRAM tRC:
122 * [04:00] DRAM tRAS:
123 * TIME_CFG2
124 * [31:28] DRAM tRCD:
125 * [27:23] DRAM tFAW:
126 * [22:19] DRAM tRTW1:
127 * [18:15] DRAM tCCD:
128 * [14:10] DRAM tRTP:
129 * [09:05] DRAM tRP:
130 * [04:00] DRAM tRPA
131 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400132#ifdef CONFIG_ADS5121_REV2
Grzegorz Bernacki37e3c622008-01-28 10:15:02 +0100133#define CFG_MDDRC_SYS_CFG 0xF8604A00
134#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
Martha Marxf31c49d2008-05-29 14:23:25 -0400135#define CFG_MDDRC_TIME_CFG1 0x54EC1168
136#define CFG_MDDRC_TIME_CFG2 0x35210864
137#else
138#define CFG_MDDRC_SYS_CFG 0xFA804A00
139#define CFG_MDDRC_SYS_CFG_RUN 0xEA804A00
140#define CFG_MDDRC_TIME_CFG1 0x68EC1168
141#define CFG_MDDRC_TIME_CFG2 0x34310864
142#endif
Grzegorz Bernacki37e3c622008-01-28 10:15:02 +0100143#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
144#define CFG_MDDRC_TIME_CFG0 0x00003D2E
145#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200146
147#define CFG_MICRON_NOP 0x01380000
148#define CFG_MICRON_PCHG_ALL 0x01100400
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200149#define CFG_MICRON_EM2 0x01020000
150#define CFG_MICRON_EM3 0x01030000
151#define CFG_MICRON_EN_DLL 0x01010000
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200152#define CFG_MICRON_RFSH 0x01080000
Grzegorz Bernacki37e3c622008-01-28 10:15:02 +0100153#define CFG_MICRON_INIT_DEV_OP 0x01000432
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200154#define CFG_MICRON_OCD_DEFAULT 0x01010780
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200155
156/* DDR Priority Manager Configuration */
York Sun0e1bad42008-05-05 10:20:01 -0500157#define CFG_MDDRCGRP_PM_CFG1 0x00077777
158#define CFG_MDDRCGRP_PM_CFG2 0x00000000
159#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
160#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC
161#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA
162#define CFG_MDDRCGRP_LUT1_MU 0x66666666
163#define CFG_MDDRCGRP_LUT1_ML 0x55555555
164#define CFG_MDDRCGRP_LUT2_MU 0x44444444
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200165#define CFG_MDDRCGRP_LUT2_ML 0x44444444
York Sun0e1bad42008-05-05 10:20:01 -0500166#define CFG_MDDRCGRP_LUT3_MU 0x55555555
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200167#define CFG_MDDRCGRP_LUT3_ML 0x55555558
York Sun0e1bad42008-05-05 10:20:01 -0500168#define CFG_MDDRCGRP_LUT4_MU 0x11111111
169#define CFG_MDDRCGRP_LUT4_ML 0x11111122
170#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa
171#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa
172#define CFG_MDDRCGRP_LUT1_AU 0x66666666
173#define CFG_MDDRCGRP_LUT1_AL 0x66666666
174#define CFG_MDDRCGRP_LUT2_AU 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200175#define CFG_MDDRCGRP_LUT2_AL 0x11111111
York Sun0e1bad42008-05-05 10:20:01 -0500176#define CFG_MDDRCGRP_LUT3_AU 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200177#define CFG_MDDRCGRP_LUT3_AL 0x11111111
York Sun0e1bad42008-05-05 10:20:01 -0500178#define CFG_MDDRCGRP_LUT4_AU 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200179#define CFG_MDDRCGRP_LUT4_AL 0x11111111
180
181/*
182 * NOR FLASH on the Local Bus
183 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400184#undef CONFIG_BKUP_FLASH
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200185#define CFG_FLASH_CFI /* use the Common Flash Interface */
186#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
Martha Marxf31c49d2008-05-29 14:23:25 -0400187#ifdef CONFIG_BKUP_FLASH
188#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */
189#define CFG_FLASH_SIZE 0x00800000 /* max flash size in bytes */
190#else
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200191#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
192#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400193#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200194#define CFG_FLASH_USE_BUFFER_WRITE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200195#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200196#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200197#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
198
199#undef CFG_FLASH_CHECKSUM
200
201/*
202 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
203 * window is 64KB
204 */
205#define CFG_CPLD_BASE 0x82000000
206#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
207
208#define CFG_SRAM_BASE 0x30000000
209#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
210
211#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
212#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
213
214/* Use SRAM for initial stack */
215#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
216#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
217
218#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
219#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
220#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
221
222#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
223#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
York Sun0e1bad42008-05-05 10:20:01 -0500224#ifdef CONFIG_FSL_DIU_FB
225#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
226#else
227#define CFG_MALLOC_LEN (512 * 1024)
228#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200229
230/*
231 * Serial Port
232 */
233#define CONFIG_CONS_INDEX 1
234#undef CONFIG_SERIAL_SOFTWARE_FIFO
235
236/*
237 * Serial console configuration
238 */
239#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
240#if CONFIG_PSC_CONSOLE != 3
241#error CONFIG_PSC_CONSOLE must be 3
242#endif
243#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
244#define CFG_BAUDRATE_TABLE \
245 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
246
247#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
248#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
249#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
250#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
251
252#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
253/* Use the HUSH parser */
254#define CFG_HUSH_PARSER
255#ifdef CFG_HUSH_PARSER
256#define CFG_PROMPT_HUSH_PS2 "> "
257#endif
258
John Rigby5f91db72008-02-26 09:38:14 -0700259/*
260 * PCI
261 */
262#ifdef CONFIG_PCI
263
264/*
265 * General PCI
266 */
267#define CFG_PCI_MEM_BASE 0xA0000000
268#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
269#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
270#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
271#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
272#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
273#define CFG_PCI_IO_BASE 0x00000000
274#define CFG_PCI_IO_PHYS 0x84000000
275#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */
276
277
278#define CONFIG_PCI_PNP /* do pci plug-and-play */
279
280#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
281
282#endif
283
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200284/* I2C */
285#define CONFIG_HARD_I2C /* I2C with hardware support */
286#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
287#define CONFIG_I2C_MULTI_BUS
288#define CONFIG_I2C_CMD_TREE
289#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
290#define CFG_I2C_SLAVE 0x7F
291#if 0
Wolfgang Denkcf5933b2007-12-06 10:21:03 +0100292#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200293#endif
294
295/*
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200296 * EEPROM configuration
297 */
298#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
299#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
Wolfgang Denkde74b9e2007-10-13 21:15:39 +0200300#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200301#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
302
303/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200304 * Ethernet configuration
305 */
306#define CONFIG_MPC512x_FEC 1
307#define CONFIG_NET_MULTI
308#define CONFIG_PHY_ADDR 0x1
309#define CONFIG_MII 1 /* MII PHY management */
Martha Marxf31c49d2008-05-29 14:23:25 -0400310#define CONFIG_FEC_AN_TIMEOUT 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200311
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200312/*
313 * Configure on-board RTC
314 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400315#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200316#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200317
318/*
319 * Environment
320 */
321#define CFG_ENV_IS_IN_FLASH 1
322/* This has to be a multiple of the Flash sector size */
323#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
324#define CFG_ENV_SIZE 0x2000
Martha Marxf31c49d2008-05-29 14:23:25 -0400325#ifdef CONFIG_BKUP_FLASH
326#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
327#else
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200328#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400329#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200330
331/* Address and size of Redundant Environment Sector */
332#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
333#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
334
335#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
336#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
337
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200338#include <config_cmd_default.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200339
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200340#define CONFIG_CMD_ASKENV
341#define CONFIG_CMD_DHCP
342#define CONFIG_CMD_I2C
343#define CONFIG_CMD_MII
344#define CONFIG_CMD_NFS
345#define CONFIG_CMD_PING
346#define CONFIG_CMD_REGINFO
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200347#define CONFIG_CMD_EEPROM
Martha Marxf31c49d2008-05-29 14:23:25 -0400348#define CONFIG_CMD_DATE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200349
350#if defined(CONFIG_PCI)
351#define CONFIG_CMD_PCI
352#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200353
354/*
355 * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
356 * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
357 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
358 * to chapter 36 of the MPC5121e Reference Manual.
359 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100360/* #define CONFIG_WATCHDOG */ /* enable watchdog */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200361#define CFG_WATCHDOG_VALUE 0xFFFF
362
363 /*
364 * Miscellaneous configurable options
365 */
366#define CFG_LONGHELP /* undef to save memory */
367#define CFG_LOAD_ADDR 0x2000000 /* default load address */
368#define CFG_PROMPT "=> " /* Monitor Command Prompt */
369
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200370#ifdef CONFIG_CMD_KGDB
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100371 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200372#else
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100373 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200374#endif
375
376
377#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
378#define CFG_MAXARGS 16 /* max number of command args */
379#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
380#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
381
382/*
383 * For booting Linux, the board info and command line data
384 * have to be in the first 8 MB of memory, since this is
385 * the maximum mapped by the Linux kernel during initialization.
386 */
387#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
388
389/* Cache Configuration */
390#define CFG_DCACHE_SIZE 32768
391#define CFG_CACHELINE_SIZE 32
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200392#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200393#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
394#endif
395
396#define CFG_HID0_INIT 0x000000000
397#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
398#define CFG_HID2 HID2_HBE
399
Becky Bruce31d82672008-05-08 19:02:12 -0500400#define CONFIG_HIGH_BATS 1 /* High BATs supported */
401
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200402/*
403 * Internal Definitions
404 *
405 * Boot Flags
406 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100407#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
408#define BOOTFLAG_WARM 0x02 /* Software reboot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200409
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200410#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200411#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
412#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
413#endif
414
415/*
416 * Environment Configuration
417 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100418#define CONFIG_TIMESTAMP
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200419
420#define CONFIG_HOSTNAME ads5121
Wolfgang Denk8d103072008-01-13 23:37:50 +0100421#define CONFIG_BOOTFILE ads5121/uImage
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100422#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200423
Wolfgang Denk8d103072008-01-13 23:37:50 +0100424#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200425
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200426#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200427#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
428
429#define CONFIG_BAUDRATE 115200
430
431#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100432 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200433 "echo"
434
435#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100436 "u-boot_addr_r=200000\0" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100437 "kernel_addr_r=300000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100438 "fdt_addr_r=400000\0" \
439 "ramdisk_addr_r=500000\0" \
440 "u-boot_addr=FFF00000\0" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100441 "kernel_addr=FC040000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100442 "fdt_addr=FC2C0000\0" \
443 "ramdisk_addr=FC300000\0" \
444 "ramdiskfile=ads5121/uRamdisk\0" \
445 "fdtfile=ads5121/ads5121.dtb\0" \
446 "u-boot=ads5121/u-boot.bin\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200447 "netdev=eth0\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100448 "consdev=ttyPSC0\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200449 "nfsargs=setenv bootargs root=/dev/nfs rw " \
450 "nfsroot=${serverip}:${rootpath}\0" \
451 "ramargs=setenv bootargs root=/dev/ram rw\0" \
452 "addip=setenv bootargs ${bootargs} " \
453 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
454 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100455 "addtty=setenv bootargs ${bootargs} " \
456 "console=${consdev},${baudrate}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200457 "flash_nfs=run nfsargs addip addtty;" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200458 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200459 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100460 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
461 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
462 "tftp ${fdt_addr_r} ${fdtfile};" \
463 "run nfsargs addip addtty;" \
464 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
465 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
466 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200467 "tftp ${fdt_addr_r} ${fdtfile};" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100468 "run ramargs addip addtty;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100469 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
Detlev Zundela99715b2008-04-18 14:50:01 +0200470 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100471 "update=protect off ${u-boot_addr} +${filesize};" \
472 "era ${u-boot_addr} +${filesize};" \
473 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
474 "upd=run load update\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200475 ""
476
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200477#define CONFIG_BOOTCOMMAND "run flash_self"
478
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100479#define CONFIG_OF_LIBFDT 1
480#define CONFIG_OF_BOARD_SETUP 1
481
482#define OF_CPU "PowerPC,5121@0"
John Rigbyac915282008-01-30 13:36:57 -0700483#define OF_SOC "soc@80000000"
484#define OF_SOC_OLD "soc5121@80000000"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100485#define OF_TBCLK (bd->bi_busfreq / 4)
John Rigbyac915282008-01-30 13:36:57 -0700486#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100487
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200488#endif /* __CONFIG_H */