blob: f2ed16a216f69c34a554876e827b199933c9acf4 [file] [log] [blame]
Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 */
wdenk0442ed82002-11-03 10:24:00 +00004
5#ifndef __PPC405_H__
6#define __PPC405_H__
7
Grant Ericksonc821b5f2008-05-22 14:44:14 -07008/* Define bits and masks for real-mode storage attribute control registers */
9#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
10#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
11
Niklaus Gigerdbcc3572009-10-04 20:04:22 +020012#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
Stefan Roese9b94ac62007-10-31 17:55:58 +010013
Stefan Roese5e7abce2010-09-11 09:31:43 +020014/* DCR registers */
15#define PLB0_ACR 0x0087
16
Stefan Roeseafabb492010-09-12 06:21:37 +020017/* SDR registers */
Stefan Roesed1c3b272009-09-09 16:25:29 +020018#define SDR0_PINSTP 0x0040
Stefan Roesedbbd1252007-10-05 17:10:59 +020019
Stefan Roeseafabb492010-09-12 06:21:37 +020020/* CPR registers */
21#define CPR0_CLKUPD 0x0020
22#define CPR0_PLLC 0x0040
23#define CPR0_PLLD 0x0060
24#define CPR0_CPUD 0x0080
25#define CPR0_PLBD 0x00a0
26#define CPR0_OPBD0 0x00c0
27#define CPR0_PERD 0x00e0
Stefan Roesedbbd1252007-10-05 17:10:59 +020028
Stefan Roeseafabb492010-09-12 06:21:37 +020029/*
30 * DMA
31 */
32#define DMA_DCR_BASE 0x0100
33#define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */
34#define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */
35#define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */
36#define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */
37#define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */
38#define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */
39#define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */
40#define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */
41#define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */
42#define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */
43#define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */
44#define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */
45#define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */
46#define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */
47#define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */
48#define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */
49#define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */
50#define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */
51#define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */
52#define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */
53#define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */
54#define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/
55#define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */
Stefan Roesedbbd1252007-10-05 17:10:59 +020056
wdenk0442ed82002-11-03 10:24:00 +000057#endif /* __PPC405_H__ */