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Stefan Roese5e7abce2010-09-11 09:31:43 +02001/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese5e7abce2010-09-11 09:31:43 +02006 */
7
8#ifndef _PPC405EP_H_
9#define _PPC405EP_H_
10
11#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
12
Stefan Roeseafabb492010-09-12 06:21:37 +020013/* Memory mapped register */
Stefan Roese550650d2010-09-20 16:05:31 +020014#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
15
16#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
17#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
18
19#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
Stefan Roeseafabb492010-09-12 06:21:37 +020020
21/* DCR */
22#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
23#define OCM0_DSARC 0x001a /* OCM D-side address compare */
24#define OCM0_DSCNTL 0x001b /* OCM D-side control */
25#define CPC0_PLLMR0 0x00f0 /* PLL mode register 0 */
26#define CPC0_BOOT 0x00f1 /* Clock status register */
27#define CPC0_CR1 0x00f2 /* Chip Control 1 register */
28#define CPC0_EPCTL 0x00f3 /* EMAC to PHY control register */
29#define CPC0_PLLMR1 0x00f4 /* PLL mode register 1 */
30#define CPC0_UCR 0x00f5 /* UART control register */
31#define CPC0_SRR 0x00f6 /* Soft Reset register */
32#define CPC0_PCI 0x00f9 /* PCI control register */
33
34/* Defines for CPC0_EPCTL register */
35#define CPC0_EPCTL_E0NFE 0x80000000
36#define CPC0_EPCTL_E1NFE 0x40000000
37
38/* Defines for CPC0_PCI Register */
39#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
40#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
41#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
42
43/* Defines for CPC0_BOOR Register */
44#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
45
46/* Bit definitions */
47#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
48#define PLLMR0_CPU_DIV_BYPASS 0x00000000
49#define PLLMR0_CPU_DIV_2 0x00100000
50#define PLLMR0_CPU_DIV_3 0x00200000
51#define PLLMR0_CPU_DIV_4 0x00300000
52
53#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
54#define PLLMR0_CPU_PLB_DIV_1 0x00000000
55#define PLLMR0_CPU_PLB_DIV_2 0x00010000
56#define PLLMR0_CPU_PLB_DIV_3 0x00020000
57#define PLLMR0_CPU_PLB_DIV_4 0x00030000
58
59#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
60#define PLLMR0_OPB_PLB_DIV_1 0x00000000
61#define PLLMR0_OPB_PLB_DIV_2 0x00001000
62#define PLLMR0_OPB_PLB_DIV_3 0x00002000
63#define PLLMR0_OPB_PLB_DIV_4 0x00003000
64
65#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
66#define PLLMR0_EXB_PLB_DIV_2 0x00000000
67#define PLLMR0_EXB_PLB_DIV_3 0x00000100
68#define PLLMR0_EXB_PLB_DIV_4 0x00000200
69#define PLLMR0_EXB_PLB_DIV_5 0x00000300
70
71#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
72#define PLLMR0_MAL_PLB_DIV_1 0x00000000
73#define PLLMR0_MAL_PLB_DIV_2 0x00000010
74#define PLLMR0_MAL_PLB_DIV_3 0x00000020
75#define PLLMR0_MAL_PLB_DIV_4 0x00000030
76
77#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
78#define PLLMR0_PCI_PLB_DIV_1 0x00000000
79#define PLLMR0_PCI_PLB_DIV_2 0x00000001
80#define PLLMR0_PCI_PLB_DIV_3 0x00000002
81#define PLLMR0_PCI_PLB_DIV_4 0x00000003
82
83#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
84#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
85#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
86
87#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
88#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
89#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
90
91/* Defines for CPC0_PLLMR1 Register fields */
92#define PLL_ACTIVE 0x80000000
93#define CPC0_PLLMR1_SSCS 0x80000000
94#define PLL_RESET 0x40000000
95#define CPC0_PLLMR1_PLLR 0x40000000
96/* Feedback multiplier */
97#define PLL_FBKDIV 0x00F00000
98#define CPC0_PLLMR1_FBDV 0x00F00000
99#define PLL_FBKDIV_16 0x00000000
100#define PLL_FBKDIV_1 0x00100000
101#define PLL_FBKDIV_2 0x00200000
102#define PLL_FBKDIV_3 0x00300000
103#define PLL_FBKDIV_4 0x00400000
104#define PLL_FBKDIV_5 0x00500000
105#define PLL_FBKDIV_6 0x00600000
106#define PLL_FBKDIV_7 0x00700000
107#define PLL_FBKDIV_8 0x00800000
108#define PLL_FBKDIV_9 0x00900000
109#define PLL_FBKDIV_10 0x00A00000
110#define PLL_FBKDIV_11 0x00B00000
111#define PLL_FBKDIV_12 0x00C00000
112#define PLL_FBKDIV_13 0x00D00000
113#define PLL_FBKDIV_14 0x00E00000
114#define PLL_FBKDIV_15 0x00F00000
115/* Forward A divisor */
116#define PLL_FWDDIVA 0x00070000
117#define CPC0_PLLMR1_FWDVA 0x00070000
118#define PLL_FWDDIVA_8 0x00000000
119#define PLL_FWDDIVA_7 0x00010000
120#define PLL_FWDDIVA_6 0x00020000
121#define PLL_FWDDIVA_5 0x00030000
122#define PLL_FWDDIVA_4 0x00040000
123#define PLL_FWDDIVA_3 0x00050000
124#define PLL_FWDDIVA_2 0x00060000
125#define PLL_FWDDIVA_1 0x00070000
126/* Forward B divisor */
127#define PLL_FWDDIVB 0x00007000
128#define CPC0_PLLMR1_FWDVB 0x00007000
129#define PLL_FWDDIVB_8 0x00000000
130#define PLL_FWDDIVB_7 0x00001000
131#define PLL_FWDDIVB_6 0x00002000
132#define PLL_FWDDIVB_5 0x00003000
133#define PLL_FWDDIVB_4 0x00004000
134#define PLL_FWDDIVB_3 0x00005000
135#define PLL_FWDDIVB_2 0x00006000
136#define PLL_FWDDIVB_1 0x00007000
137/* PLL tune bits */
138#define PLL_TUNE_MASK 0x000003FF
139#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
140#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
141#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
142#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
143#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
144#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
145#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
146
147/* Defines for CPC0_PLLMR0 Register fields */
148/* CPU divisor */
149#define PLL_CPUDIV 0x00300000
150#define CPC0_PLLMR0_CCDV 0x00300000
151#define PLL_CPUDIV_1 0x00000000
152#define PLL_CPUDIV_2 0x00100000
153#define PLL_CPUDIV_3 0x00200000
154#define PLL_CPUDIV_4 0x00300000
155/* PLB divisor */
156#define PLL_PLBDIV 0x00030000
157#define CPC0_PLLMR0_CBDV 0x00030000
158#define PLL_PLBDIV_1 0x00000000
159#define PLL_PLBDIV_2 0x00010000
160#define PLL_PLBDIV_3 0x00020000
161#define PLL_PLBDIV_4 0x00030000
162/* OPB divisor */
163#define PLL_OPBDIV 0x00003000
164#define CPC0_PLLMR0_OPDV 0x00003000
165#define PLL_OPBDIV_1 0x00000000
166#define PLL_OPBDIV_2 0x00001000
167#define PLL_OPBDIV_3 0x00002000
168#define PLL_OPBDIV_4 0x00003000
169/* EBC divisor */
170#define PLL_EXTBUSDIV 0x00000300
171#define CPC0_PLLMR0_EPDV 0x00000300
172#define PLL_EXTBUSDIV_2 0x00000000
173#define PLL_EXTBUSDIV_3 0x00000100
174#define PLL_EXTBUSDIV_4 0x00000200
175#define PLL_EXTBUSDIV_5 0x00000300
176/* MAL divisor */
177#define PLL_MALDIV 0x00000030
178#define CPC0_PLLMR0_MPDV 0x00000030
179#define PLL_MALDIV_1 0x00000000
180#define PLL_MALDIV_2 0x00000010
181#define PLL_MALDIV_3 0x00000020
182#define PLL_MALDIV_4 0x00000030
183/* PCI divisor */
184#define PLL_PCIDIV 0x00000003
185#define CPC0_PLLMR0_PPFD 0x00000003
186#define PLL_PCIDIV_1 0x00000000
187#define PLL_PCIDIV_2 0x00000001
188#define PLL_PCIDIV_3 0x00000002
189#define PLL_PCIDIV_4 0x00000003
190
191/*
192 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
193 * assuming a 33.3MHz input clock to the 405EP.
194 */
195#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
196 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
197 PLL_MALDIV_1 | PLL_PCIDIV_4)
198#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
199 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
200 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
201
202#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
203 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
204 PLL_MALDIV_1 | PLL_PCIDIV_4)
205#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
206 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
207 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
208#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
209 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
210 PLL_MALDIV_1 | PLL_PCIDIV_4)
211#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
212 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
213 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
214#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
215 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
216 PLL_MALDIV_1 | PLL_PCIDIV_4)
217#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
218 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
219 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
220#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
221 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
222 PLL_MALDIV_1 | PLL_PCIDIV_2)
223#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
224 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
225 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
226#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
227 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
228 PLL_MALDIV_1 | PLL_PCIDIV_3)
229#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
230 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
231 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
232#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
233 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
234 PLL_MALDIV_1 | PLL_PCIDIV_1)
235#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
236 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
237 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
238
Stefan Roese5e7abce2010-09-11 09:31:43 +0200239#endif /* _PPC405EP_H_ */