blob: 3ca64b980d42e81c6ac290a92def9aa41462c911 [file] [log] [blame]
Gary Jennejohn041a2552007-08-31 14:29:04 +02001/*
2 * (C) Copyright 2007
3 * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Gary Jennejohn041a2552007-08-31 14:29:04 +02006 */
7/* sil680.c - ide support functions for the Sil0680A controller */
8
9/*
10 * The following parameters must be defined in the configuration file
11 * of the target board:
12 *
Jean-Christophe PLAGNIOL-VILLARD1a028062008-08-13 01:40:39 +020013 * #define CONFIG_IDE_SIL680
Gary Jennejohn041a2552007-08-31 14:29:04 +020014 *
15 * #define CONFIG_PCI_PNP
16 * NOTE it may also be necessary to define this if the default of 8 is
17 * incorrect for the target board (e.g. the sequoia board requires 0).
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020018 * #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
Gary Jennejohn041a2552007-08-31 14:29:04 +020019 *
20 * #define CONFIG_CMD_IDE
21 * #undef CONFIG_IDE_8xx_DIRECT
22 * #undef CONFIG_IDE_LED
23 * #undef CONFIG_IDE_RESET
24 * #define CONFIG_IDE_PREINIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025 * #define CONFIG_SYS_IDE_MAXBUS 2 - modify to suit
26 * #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) - modify to suit
27 * #define CONFIG_SYS_ATA_BASE_ADDR 0
28 * #define CONFIG_SYS_ATA_IDE0_OFFSET 0
29 * #define CONFIG_SYS_ATA_IDE1_OFFSET 0
30 * #define CONFIG_SYS_ATA_DATA_OFFSET 0
31 * #define CONFIG_SYS_ATA_REG_OFFSET 0
32 * #define CONFIG_SYS_ATA_ALT_OFFSET 0x0004
Gary Jennejohn041a2552007-08-31 14:29:04 +020033 *
34 * The mapping for PCI IO-space.
35 * NOTE this is the value for the sequoia board. Modify to suit.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 * #define CONFIG_SYS_PCI0_IO_SPACE 0xE8000000
Gary Jennejohn041a2552007-08-31 14:29:04 +020037 */
38
39#include <common.h>
Gary Jennejohn041a2552007-08-31 14:29:04 +020040#include <ata.h>
41#include <ide.h>
42#include <pci.h>
43
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
Gary Jennejohn041a2552007-08-31 14:29:04 +020045
46int ide_preinit (void)
47{
48 int status;
49 pci_dev_t devbusfn;
50 int l;
51
52 status = 1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
Gary Jennejohn041a2552007-08-31 14:29:04 +020054 ide_bus_offset[l] = -ATA_STATUS;
55 }
56 devbusfn = pci_find_device (0x1095, 0x0680, 0);
57 if (devbusfn != -1) {
58 status = 0;
59
60 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
61 (u32 *) &ide_bus_offset[0]);
62 ide_bus_offset[0] &= 0xfffffff8;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
Gary Jennejohn041a2552007-08-31 14:29:04 +020064 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
65 (u32 *) &ide_bus_offset[1]);
66 ide_bus_offset[1] &= 0xfffffff8;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
Gary Jennejohn041a2552007-08-31 14:29:04 +020068 /* init various things - taken from the Linux driver */
69 /* set PIO mode */
70 pci_write_config_byte(devbusfn, 0x80, 0x00);
71 pci_write_config_byte(devbusfn, 0x84, 0x00);
72 /* IDE0 */
73 pci_write_config_byte(devbusfn, 0xA1, 0x02);
74 pci_write_config_word(devbusfn, 0xA2, 0x328A);
75 pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
76 pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
77 pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
78 /* IDE1 */
79 pci_write_config_byte(devbusfn, 0xB1, 0x02);
80 pci_write_config_word(devbusfn, 0xB2, 0x328A);
81 pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
82 pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
83 pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
84 }
85 return (status);
86}
87
88void ide_set_reset (int flag) {
89 return;
90}