blob: 8de981981dc624f28c416484cb33caf3a06ee5fa [file] [log] [blame]
wdenk3bac3512003-03-12 10:41:04 +00001/*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CPC45 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8245 1
46#define CONFIG_CPC45 1
47
48
49#define CONFIG_CONS_INDEX 1
50#define CONFIG_BAUDRATE 9600
51#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
52
wdenk3bac3512003-03-12 10:41:04 +000053#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
54
55#define CONFIG_BOOTDELAY 5
56
57#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
58
59#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk49822e22004-06-19 21:19:10 +000060 CFG_CMD_BEDBUG | \
61 CFG_CMD_DATE | \
wdenk3bac3512003-03-12 10:41:04 +000062 CFG_CMD_DHCP | \
wdenk49822e22004-06-19 21:19:10 +000063 CFG_CMD_EEPROM | \
wdenke2ffd592004-12-31 09:32:47 +000064 CFG_CMD_FAT | \
65 CFG_CMD_FLASH | \
wdenk49822e22004-06-19 21:19:10 +000066 CFG_CMD_I2C | \
wdenke2ffd592004-12-31 09:32:47 +000067 CFG_CMD_IDE | \
wdenk3bac3512003-03-12 10:41:04 +000068 CFG_CMD_PCI | \
wdenk49822e22004-06-19 21:19:10 +000069 CFG_CMD_SDRAM )
wdenk3bac3512003-03-12 10:41:04 +000070
71/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
72 */
73#include <cmd_confdefs.h>
74
75
76/*
77 * Miscellaneous configurable options
78 */
79#define CFG_LONGHELP /* undef to save memory */
80#define CFG_PROMPT "=> " /* Monitor Command Prompt */
81#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
82
83#if 1
wdenk49822e22004-06-19 21:19:10 +000084#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
wdenk3bac3512003-03-12 10:41:04 +000085#endif
86#ifdef CFG_HUSH_PARSER
wdenk49822e22004-06-19 21:19:10 +000087#define CFG_PROMPT_HUSH_PS2 "> "
wdenk3bac3512003-03-12 10:41:04 +000088#endif
89
90/* Print Buffer Size
91 */
92#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
93
wdenk49822e22004-06-19 21:19:10 +000094#define CFG_MAXARGS 16 /* max number of command args */
wdenk3bac3512003-03-12 10:41:04 +000095#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
96#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
97
98/*-----------------------------------------------------------------------
99 * Start addresses for the final memory configuration
100 * (Set up by the startup code)
101 * Please note that CFG_SDRAM_BASE _must_ start at 0
102 */
103
wdenk49822e22004-06-19 21:19:10 +0000104#define CFG_SDRAM_BASE 0x00000000
wdenk3bac3512003-03-12 10:41:04 +0000105
106#if defined(CONFIG_BOOT_ROM)
wdenk49822e22004-06-19 21:19:10 +0000107#define CFG_FLASH_BASE 0xFF000000
wdenk3bac3512003-03-12 10:41:04 +0000108#else
wdenk49822e22004-06-19 21:19:10 +0000109#define CFG_FLASH_BASE 0xFF800000
wdenk3bac3512003-03-12 10:41:04 +0000110#endif
111
wdenk49822e22004-06-19 21:19:10 +0000112#define CFG_RESET_ADDRESS 0xFFF00100
wdenk3bac3512003-03-12 10:41:04 +0000113
wdenk49822e22004-06-19 21:19:10 +0000114#define CFG_EUMB_ADDR 0xFCE00000
wdenk3bac3512003-03-12 10:41:04 +0000115
wdenk49822e22004-06-19 21:19:10 +0000116#define CFG_MONITOR_BASE TEXT_BASE
wdenk3bac3512003-03-12 10:41:04 +0000117
wdenk49822e22004-06-19 21:19:10 +0000118#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
119#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk3bac3512003-03-12 10:41:04 +0000120
wdenk49822e22004-06-19 21:19:10 +0000121#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
122#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenk3bac3512003-03-12 10:41:04 +0000123
wdenk49822e22004-06-19 21:19:10 +0000124/* Maximum amount of RAM.
125 */
126#define CFG_MAX_RAM_SIZE 0x10000000
wdenk3bac3512003-03-12 10:41:04 +0000127
128
129#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
130#undef CFG_RAMBOOT
131#else
132#define CFG_RAMBOOT
133#endif
134
135
136/*-----------------------------------------------------------------------
137 * Definitions for initial stack pointer and data area
138 */
139
wdenk49822e22004-06-19 21:19:10 +0000140/* Size in bytes reserved for initial data
141 */
142#define CFG_GBL_DATA_SIZE 128
wdenk3bac3512003-03-12 10:41:04 +0000143
wdenk49822e22004-06-19 21:19:10 +0000144#define CFG_INIT_RAM_ADDR 0x40000000
145#define CFG_INIT_RAM_END 0x1000
146#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenk3bac3512003-03-12 10:41:04 +0000147
148/*
149 * NS16550 Configuration
150 */
stroese53cf9432003-06-05 15:39:44 +0000151#define CFG_NS16550
wdenk3bac3512003-03-12 10:41:04 +0000152#define CFG_NS16550_SERIAL
153
154#define CFG_NS16550_REG_SIZE 1
155
156#define CFG_NS16550_CLK get_bus_freq(0)
157
158#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
159#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
wdenk49822e22004-06-19 21:19:10 +0000160#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
161
162/*
163 * I2C configuration
164 */
165#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
166
167#define CFG_I2C_SPEED 100000 /* 100 kHz */
168#define CFG_I2C_SLAVE 0x7F
169
170/*
171 * RTC configuration
172 */
173#define CONFIG_RTC_PCF8563
174#define CFG_I2C_RTC_ADDR 0x51
175
176/*
177 * EEPROM configuration
178 */
179#define CFG_I2C_EEPROM_ADDR 0x58
180#define CFG_I2C_EEPROM_ADDR_LEN 1
181#define CFG_EEPROM_PAGE_WRITE_BITS 4
182#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
183#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
wdenk3bac3512003-03-12 10:41:04 +0000184
185/*
186 * Low Level Configuration Settings
187 * (address mappings, register initial values, etc.)
188 * You should know what you are doing if you make changes here.
189 * For the detail description refer to the MPC8240 user's manual.
190 */
191
wdenk49822e22004-06-19 21:19:10 +0000192#define CONFIG_SYS_CLK_FREQ 33000000
193#define CFG_HZ 1000
194
195
196/* Bit-field values for MCCR1.
197 */
198#define CFG_ROMNAL 0
199#define CFG_ROMFAL 8
200
201#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
202#define CFG_BANK1_ROW 0
203#define CFG_BANK2_ROW 0
204#define CFG_BANK3_ROW 0
205#define CFG_BANK4_ROW 0
206#define CFG_BANK5_ROW 0
207#define CFG_BANK6_ROW 0
208#define CFG_BANK7_ROW 0
209
210/* Bit-field values for MCCR2.
wdenk3bac3512003-03-12 10:41:04 +0000211 */
stroese53cf9432003-06-05 15:39:44 +0000212
wdenk49822e22004-06-19 21:19:10 +0000213#define CFG_REFINT 0x2ec
wdenk3bac3512003-03-12 10:41:04 +0000214
wdenk49822e22004-06-19 21:19:10 +0000215/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
216 */
217#define CFG_BSTOPRE 160
wdenk3bac3512003-03-12 10:41:04 +0000218
wdenk49822e22004-06-19 21:19:10 +0000219/* Bit-field values for MCCR3.
220 */
221#define CFG_REFREC 2 /* Refresh to activate interval */
222#define CFG_RDLAT 0 /* Data latancy from read command */
wdenk3bac3512003-03-12 10:41:04 +0000223
wdenk49822e22004-06-19 21:19:10 +0000224/* Bit-field values for MCCR4.
225 */
226#define CFG_PRETOACT 2 /* Precharge to activate interval */
227#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
228#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
229#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
230#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
231#define CFG_ACTORW 2
wdenk3bac3512003-03-12 10:41:04 +0000232#define CFG_REGISTERD_TYPE_BUFFER 1
wdenk49822e22004-06-19 21:19:10 +0000233#define CFG_EXTROM 0
234#define CFG_REGDIMM 0
wdenk3bac3512003-03-12 10:41:04 +0000235
236/* Memory bank settings.
237 * Only bits 20-29 are actually used from these vales to set the
238 * start/end addresses. The upper two bits will always be 0, and the lower
239 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
240 * address. Refer to the MPC8240 book.
241 */
242
wdenk49822e22004-06-19 21:19:10 +0000243#define CFG_BANK0_START 0x00000000
244#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
245#define CFG_BANK0_ENABLE 1
246#define CFG_BANK1_START 0x3ff00000
247#define CFG_BANK1_END 0x3fffffff
248#define CFG_BANK1_ENABLE 0
249#define CFG_BANK2_START 0x3ff00000
250#define CFG_BANK2_END 0x3fffffff
251#define CFG_BANK2_ENABLE 0
252#define CFG_BANK3_START 0x3ff00000
253#define CFG_BANK3_END 0x3fffffff
254#define CFG_BANK3_ENABLE 0
255#define CFG_BANK4_START 0x3ff00000
256#define CFG_BANK4_END 0x3fffffff
257#define CFG_BANK4_ENABLE 0
258#define CFG_BANK5_START 0x3ff00000
259#define CFG_BANK5_END 0x3fffffff
260#define CFG_BANK5_ENABLE 0
261#define CFG_BANK6_START 0x3ff00000
262#define CFG_BANK6_END 0x3fffffff
263#define CFG_BANK6_ENABLE 0
264#define CFG_BANK7_START 0x3ff00000
265#define CFG_BANK7_END 0x3fffffff
266#define CFG_BANK7_ENABLE 0
wdenk3bac3512003-03-12 10:41:04 +0000267
wdenk49822e22004-06-19 21:19:10 +0000268#define CFG_ODCR 0xff
269#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
270 /* currently accessed page in memory */
271 /* see 8240 book for details */
wdenk3bac3512003-03-12 10:41:04 +0000272
273#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
274#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
275
276#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
277#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
278
279#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
280#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
281
282#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
283#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
284
285#define CFG_DBAT0L CFG_IBAT0L
286#define CFG_DBAT0U CFG_IBAT0U
287#define CFG_DBAT1L CFG_IBAT1L
288#define CFG_DBAT1U CFG_IBAT1U
289#define CFG_DBAT2L CFG_IBAT2L
290#define CFG_DBAT2U CFG_IBAT2U
291#define CFG_DBAT3L CFG_IBAT3L
292#define CFG_DBAT3U CFG_IBAT3U
293
294/*
295 * For booting Linux, the board info and command line data
296 * have to be in the first 8 MB of memory, since this is
297 * the maximum mapped by the Linux kernel during initialization.
298 */
wdenk49822e22004-06-19 21:19:10 +0000299#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk3bac3512003-03-12 10:41:04 +0000300
301/*-----------------------------------------------------------------------
302 * FLASH organization
303 */
304#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
305#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
306#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
307#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
308#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
309
310 /* Warining: environment is not EMBEDDED in the ppcboot code.
311 * It's stored in flash separately.
312 */
313#define CFG_ENV_IS_IN_FLASH 1
314
wdenk49822e22004-06-19 21:19:10 +0000315#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000)
wdenk3bac3512003-03-12 10:41:04 +0000316#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
317#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
318#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
319
320/*-----------------------------------------------------------------------
321 * Cache Configuration
322 */
323#define CFG_CACHELINE_SIZE 32
324#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
325# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
326#endif
327
328/*
329 * Internal Definitions
330 *
331 * Boot Flags
332 */
333#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
334#define BOOTFLAG_WARM 0x02 /* Software reboot */
335
336
wdenk49822e22004-06-19 21:19:10 +0000337#define SRAM_BASE 0x80000000 /* SRAM base address */
338#define SRAM_END 0x801FFFFF
wdenk3bac3512003-03-12 10:41:04 +0000339
wdenk49822e22004-06-19 21:19:10 +0000340/*----------------------------------------------------------------------*/
341/* CPC45 Memory Map */
342/*----------------------------------------------------------------------*/
343#define SRAM_BASE 0x80000000 /* SRAM base address */
344#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
345#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
346#define BCSR_BASE 0x80600000 /* board control / status registers */
347#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
wdenke2ffd592004-12-31 09:32:47 +0000348#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
wdenk49822e22004-06-19 21:19:10 +0000349#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
wdenk3bac3512003-03-12 10:41:04 +0000350
351
352/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000353/* CPC45 Control/Status Registers */
wdenk3bac3512003-03-12 10:41:04 +0000354/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000355#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
356#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
357#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
358#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
359#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
360#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
361#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
362#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
363#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
364#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
wdenk3bac3512003-03-12 10:41:04 +0000365
366/* IRQ_ENA_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000367#define I_ENA_1_IERA 0x80 /* INTA enable */
368#define I_ENA_1_IERB 0x40 /* INTB enable */
369#define I_ENA_1_IERC 0x20 /* INTC enable */
370#define I_ENA_1_IERD 0x10 /* INTD enable */
wdenk3bac3512003-03-12 10:41:04 +0000371
372/* IRQ_STAT_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000373#define I_STAT_1_INTA 0x80 /* INTA status */
374#define I_STAT_1_INTB 0x40 /* INTB status */
375#define I_STAT_1_INTC 0x20 /* INTC status */
376#define I_STAT_1_INTD 0x10 /* INTD status */
wdenk3bac3512003-03-12 10:41:04 +0000377
378/* IRQ_ENA_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000379#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
380#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
381#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
382#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
383#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
384#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
385#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
386#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
wdenk3bac3512003-03-12 10:41:04 +0000387
388/* IRQ_STAT_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000389#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
390#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
391#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
392#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
393#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
394#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
395#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
396#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
wdenk3bac3512003-03-12 10:41:04 +0000397
398/* BOARD_CTRL bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000399#define USER_LEDS 2 /* 2 user LEDs */
wdenk3bac3512003-03-12 10:41:04 +0000400
401#if (USER_LEDS == 4)
wdenk49822e22004-06-19 21:19:10 +0000402#define B_CTRL_WRSE 0x80
403#define B_CTRL_KRSE 0x40
404#define B_CTRL_FWRE 0x20 /* Flash write enable */
405#define B_CTRL_FWPT 0x10 /* Flash write protect */
406#define B_CTRL_LED3 0x08 /* LED 3 control */
407#define B_CTRL_LED2 0x04 /* LED 2 control */
408#define B_CTRL_LED1 0x02 /* LED 1 control */
409#define B_CTRL_LED0 0x01 /* LED 0 control */
wdenk3bac3512003-03-12 10:41:04 +0000410#else
wdenk49822e22004-06-19 21:19:10 +0000411#define B_CTRL_WRSE 0x80
412#define B_CTRL_KRSE 0x40
413#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
414#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
415#define B_CTRL_LED1 0x08 /* LED 1 control */
416#define B_CTRL_LED0 0x04 /* LED 0 control */
417#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
418#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
wdenk3bac3512003-03-12 10:41:04 +0000419#endif
420
421/* BOARD_STAT bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000422#define B_STAT_WDGE 0x80
423#define B_STAT_WDGS 0x40
424#define B_STAT_WRST 0x20
425#define B_STAT_KRST 0x10
426#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
427#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
428#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
429#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
wdenk3bac3512003-03-12 10:41:04 +0000430
431/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000432/* Display addresses */
wdenk3bac3512003-03-12 10:41:04 +0000433/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000434#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
435#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
436#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
wdenk3bac3512003-03-12 10:41:04 +0000437
wdenk49822e22004-06-19 21:19:10 +0000438#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
439#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
wdenk3bac3512003-03-12 10:41:04 +0000440
wdenk49822e22004-06-19 21:19:10 +0000441#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
442#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
443#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
444#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
445#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
446#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
447#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
448#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
wdenk3bac3512003-03-12 10:41:04 +0000449
450
451/*-----------------------------------------------------------------------
452 * PCI stuff
453 *-----------------------------------------------------------------------
454 */
455#define CONFIG_PCI /* include pci support */
wdenk49822e22004-06-19 21:19:10 +0000456#undef CONFIG_PCI_PNP
457#undef CONFIG_PCI_SCAN_SHOW
wdenk3bac3512003-03-12 10:41:04 +0000458
wdenk49822e22004-06-19 21:19:10 +0000459#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenk3bac3512003-03-12 10:41:04 +0000460
461#define CONFIG_EEPRO100
wdenk49822e22004-06-19 21:19:10 +0000462#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000463
wdenk49822e22004-06-19 21:19:10 +0000464#define PCI_ENET0_IOADDR 0x82000000
wdenk3bac3512003-03-12 10:41:04 +0000465#define PCI_ENET0_MEMADDR 0x82000000
wdenk49822e22004-06-19 21:19:10 +0000466#define PCI_PLX9030_IOADDR 0x82100000
467#define PCI_PLX9030_MEMADDR 0x82100000
wdenke2ffd592004-12-31 09:32:47 +0000468
469/*-----------------------------------------------------------------------
470 * PCMCIA stuff
471 *-----------------------------------------------------------------------
472 */
473
474#define CONFIG_I82365
475
476#define CFG_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
477#define CFG_PCMCIA_MEM_SIZE 0x1000
478
479#define CONFIG_PCMCIA_SLOT_A
480
481/*-----------------------------------------------------------------------
482 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
483 *-----------------------------------------------------------------------
484 */
485
486#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
487
488#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
489#undef CONFIG_IDE_RESET /* reset for IDE not supported */
490#define CONFIG_IDE_LED /* LED for IDE is supported */
491
492#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
493#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
494
495#define CFG_ATA_IDE0_OFFSET 0x0000
496#define CONFIG_HMI10
497
498#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
499
500#define CFG_ATA_DATA_OFFSET CFG_PCMCIA_MEM_SIZE
501
502/* Offset for normal register accesses */
503#define CFG_ATA_REG_OFFSET CFG_PCMCIA_MEM_SIZE
504
505/* Offset for alternate registers */
506#define CFG_ATA_ALT_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x400)
507
508#define CONFIG_DOS_PARTITION
509
wdenk3bac3512003-03-12 10:41:04 +0000510#endif /* __CONFIG_H */