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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 *
10 * Configuration settings for the CU824 board.
11 *
12 */
13
14/* ------------------------------------------------------------------------- */
15
16/*
17 * board/config.h - configuration options, board specific
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 * (easy to change)
26 */
27
wdenkc6097192002-11-03 00:24:07 +000028#define CONFIG_MPC8240 1
29#define CONFIG_CU824 1
30
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#define CONFIG_SYS_TEXT_BASE 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +000032
33#define CONFIG_CONS_INDEX 1
34#define CONFIG_BAUDRATE 9600
wdenkc6097192002-11-03 00:24:07 +000035
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010036#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkc6097192002-11-03 00:24:07 +000037
38#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
39#define CONFIG_BOOTDELAY 5
40
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050041/*
42 * BOOTP options
43 */
44#define CONFIG_BOOTP_SUBNETMASK
45#define CONFIG_BOOTP_GATEWAY
46#define CONFIG_BOOTP_HOSTNAME
47#define CONFIG_BOOTP_BOOTPATH
48#define CONFIG_BOOTP_BOOTFILESIZE
49
wdenkc6097192002-11-03 00:24:07 +000050
wdenk414eec32005-04-02 22:37:54 +000051#define CONFIG_TIMESTAMP /* Print image info with timestamp */
52
wdenkc6097192002-11-03 00:24:07 +000053
Jon Loeliger49cf7e82007-07-05 19:52:35 -050054/*
55 * Command line configuration.
wdenkc6097192002-11-03 00:24:07 +000056 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050057#include <config_cmd_default.h>
58
Wolfgang Denk5728be32007-08-06 01:01:49 +020059#define CONFIG_CMD_BEDBUG
Jon Loeliger49cf7e82007-07-05 19:52:35 -050060#define CONFIG_CMD_DHCP
61#define CONFIG_CMD_PCI
62#define CONFIG_CMD_NFS
63#define CONFIG_CMD_SNTP
wdenkc6097192002-11-03 00:24:07 +000064
65
66/*
67 * Miscellaneous configurable options
68 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000071
72#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenkc6097192002-11-03 00:24:07 +000074#endif
wdenkc6097192002-11-03 00:24:07 +000075
76/* Print Buffer Size
77 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenkc6097192002-11-03 00:24:07 +000079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
81#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
82#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkc6097192002-11-03 00:24:07 +000083
84/*-----------------------------------------------------------------------
85 * Start addresses for the final memory configuration
86 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +000088 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_SDRAM_BASE 0x00000000
90#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenkc6097192002-11-03 00:24:07 +000091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
wdenkc6097192002-11-03 00:24:07 +000095
Wolfgang Denk14d0a022010-10-07 21:51:12 +020096#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
99#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
102#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000103
104 /* Maximum amount of RAM.
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenkc6097192002-11-03 00:24:07 +0000107
108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
110#undef CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000111#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000113#endif
114
115
116/*-----------------------------------------------------------------------
117 * Definitions for initial stack pointer and data area
118 */
119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200121#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200122#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000123
124/*
125 * NS16550 Configuration
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_NS16550
128#define CONFIG_SYS_NS16550_SERIAL
wdenkc6097192002-11-03 00:24:07 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_NS16550_REG_SIZE 4
wdenkc6097192002-11-03 00:24:07 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_NS16550_CLK (14745600 / 2)
wdenkc6097192002-11-03 00:24:07 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_NS16550_COM1 0xFE800080
135#define CONFIG_SYS_NS16550_COM2 0xFE8000C0
wdenkc6097192002-11-03 00:24:07 +0000136
137/*
138 * Low Level Configuration Settings
139 * (address mappings, register initial values, etc.)
140 * You should know what you are doing if you make changes here.
141 * For the detail description refer to the MPC8240 user's manual.
142 */
143
144#define CONFIG_SYS_CLK_FREQ 33000000
wdenkc6097192002-11-03 00:24:07 +0000145
146 /* Bit-field values for MCCR1.
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_ROMNAL 0
149#define CONFIG_SYS_ROMFAL 7
wdenkc6097192002-11-03 00:24:07 +0000150
151 /* Bit-field values for MCCR2.
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_REFINT 430 /* Refresh interval */
wdenkc6097192002-11-03 00:24:07 +0000154
155 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BSTOPRE 192
wdenkc6097192002-11-03 00:24:07 +0000158
159 /* Bit-field values for MCCR3.
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
162#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
wdenkc6097192002-11-03 00:24:07 +0000163
164 /* Bit-field values for MCCR4.
165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
167#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
168#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
169#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
170#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
171#define CONFIG_SYS_ACTORW 2
172#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
wdenkc6097192002-11-03 00:24:07 +0000173
174/* Memory bank settings.
175 * Only bits 20-29 are actually used from these vales to set the
176 * start/end addresses. The upper two bits will always be 0, and the lower
177 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
178 * address. Refer to the MPC8240 book.
179 */
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_BANK0_START 0x00000000
182#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
183#define CONFIG_SYS_BANK0_ENABLE 1
184#define CONFIG_SYS_BANK1_START 0x3ff00000
185#define CONFIG_SYS_BANK1_END 0x3fffffff
186#define CONFIG_SYS_BANK1_ENABLE 0
187#define CONFIG_SYS_BANK2_START 0x3ff00000
188#define CONFIG_SYS_BANK2_END 0x3fffffff
189#define CONFIG_SYS_BANK2_ENABLE 0
190#define CONFIG_SYS_BANK3_START 0x3ff00000
191#define CONFIG_SYS_BANK3_END 0x3fffffff
192#define CONFIG_SYS_BANK3_ENABLE 0
193#define CONFIG_SYS_BANK4_START 0x3ff00000
194#define CONFIG_SYS_BANK4_END 0x3fffffff
195#define CONFIG_SYS_BANK4_ENABLE 0
196#define CONFIG_SYS_BANK5_START 0x3ff00000
197#define CONFIG_SYS_BANK5_END 0x3fffffff
198#define CONFIG_SYS_BANK5_ENABLE 0
199#define CONFIG_SYS_BANK6_START 0x3ff00000
200#define CONFIG_SYS_BANK6_END 0x3fffffff
201#define CONFIG_SYS_BANK6_ENABLE 0
202#define CONFIG_SYS_BANK7_START 0x3ff00000
203#define CONFIG_SYS_BANK7_END 0x3fffffff
204#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_ODCR 0xff
wdenkc6097192002-11-03 00:24:07 +0000207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
209#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
212#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
215#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
218#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
221#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
222#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
223#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
224#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
225#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
226#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
227#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000228
229/*
230 * For booting Linux, the board info and command line data
231 * have to be in the first 8 MB of memory, since this is
232 * the maximum mapped by the Linux kernel during initialization.
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000235
236/*-----------------------------------------------------------------------
237 * FLASH organization
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
240#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
wdenkc6097192002-11-03 00:24:07 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
243#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000244
245 /* Warining: environment is not EMBEDDED in the U-Boot code.
246 * It's stored in flash separately.
247 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200248#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc6097192002-11-03 00:24:07 +0000249#if 0
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200250#define CONFIG_ENV_ADDR 0xFF008000
251#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000252#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200253#define CONFIG_ENV_ADDR 0xFFFC0000
254#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
255#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
256#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000257#endif
258
259/*-----------------------------------------------------------------------
260 * Cache Configuration
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500263#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000265#endif
266
wdenkc6097192002-11-03 00:24:07 +0000267/*-----------------------------------------------------------------------
268 * PCI stuff
269 *-----------------------------------------------------------------------
270 */
271#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000272#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc6097192002-11-03 00:24:07 +0000273#undef CONFIG_PCI_PNP
274
wdenkc6097192002-11-03 00:24:07 +0000275
276#define CONFIG_TULIP
277#define CONFIG_TULIP_USE_IO
278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_ETH_DEV_FN 0x7800
280#define CONFIG_SYS_ETH_IOBASE 0x00104000
wdenkc6097192002-11-03 00:24:07 +0000281
wdenk3bac3512003-03-12 10:41:04 +0000282#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000284#define PCI_ENET0_IOADDR 0x00104000
285#define PCI_ENET0_MEMADDR 0x80000000
wdenkc6097192002-11-03 00:24:07 +0000286#endif /* __CONFIG_H */